DATASHEET TM TM Programmable Timing Control Hub for Mobile P4 954226 Systems Key Specifications: Recommended Application: CPU outputs cycle-cycle jitter < 85ps CK410M Compatible Main Clock PCI Express outputs cycle-cycle jitter < 125ps SATA outputs cycle-cycle jitter < 125ps Output Features: PCI outputs cycle-cycle jitter < 500ps 2 - 0.7V current-mode differential CPU pairs +/- 300ppm frequency accuracy on CPU, PCI Express 4 - 0.7V current-mode differential PCI Express* pairs and SATA clocks 1 - 0.7V current-mode differential CPU/PCI Express +/- 100ppm frequency accuracy on USB clocks selectable pair Features/Benefits: 1 - 0.7V current-mode differential SATA pair Supports tight ppm accuracy clocks for Serial-ATA and 1 - 0.7V current-mode differential LCDCLK/PCI Express PCI Express selectable pair Supports programmable spread percentage and 4 - PCI (33MHz) frequency 2 - PCICLK F, (33MHz) free-running Uses external 14.318MHz crystal, external crystal load 1 - USB, 48MHz caps are required for frequency tuning 1 - DOT, 96MHz, 0.7V current differential pair Supports undriven differential CPU, PCI Express pair 2 - REF, 14.318MHz in PD for power management. PEREQ pins to support PCI Express and SATA power management. MLF Pin Configuration TSSOP Pin Configuration VDDPCI 1 56 PCICLK2/REQ SEL** GND 2 55 PCI/SRC STOP PCICLK3 3 54 CPU STOP PCICLK4 4 53 REF1/FS C/TEST SEL L PCICLK5 5 52 REF0 GND 6 51 GND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 VDDPCI 7 50 X1 VDDPCI142 VDDREF ITP EN/PCICLK F0 8 49 X2 ITP EN/PCICLK F0241 SDATA **SELPCIEX LCDCLK /PCICLK F1 9 48 VDDREF **SELPCIEX LCDCLK /PCICLK F1340 SCLK Vtt PwrGd /PD 10 47 SDATA Vtt PwrGd /PD439 GND VDD48 11 46 SCLK VDD48538 CPUCLKT0 FS A/USB 48MHz 12 45 GND L FSLA/USB 48MHz637 CPUCLKC0 GND 13 44 CPUCLKT0 GND736 VDDCPU DOTT 96MHz 14 43 CPUCLKC0 ICS 954226AKLF DOTC 96MHz 15 42 VDDCPU DOTT 96MHz835 CPUCLKT1 FS B/TEST MODE 16 41 CPUCLKT1 L DOTC 96MHz934 CPUCLKC1 LCDCLK SS/PCIEX0T 17 40 CPUCLKC1 FSLB/TEST MODE 10 33 IREF LCDCLK SS/PCIEX0C 18 39 IREF LCDCLK SS/PCIEXT0 GNDA 11 32 PCIEXT119 38GNDA LCDCLK SS/PCIEXC0 12 31 VDDA PCIEXC1 20 37 VDDA PCIEXT1 13 30 CPUCLKT2 ITP/PCIEXT6 VDDPCIEX 21 36 CPUCLKT2 ITP/PCIEXT6 PCIEXC1 14 29 CPUCLKC2 ITP/PCIEXC6 PCIEXT2 22 35 CPUCLKC2 ITP/PCIEXC6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PCIEXC2 23 34 VDDPCIEX PCIEXT3 24 33 PEREQ1 */PCIEXT5 PCIEXC3 25 32 PEREQ2 */PCIEXC5 SATACLKT 26 31 PCIEXT4 SATACLKC 27 30 PCIEXC4 VDDPCIEX 28 29 GND 56-TSSOP 56-MLF * Internal Pull-Up Resistor * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ** Internal Pull-Down Resistor Table 1: Frequency Selection Table CPU PCIEX PCI REF USB DOT FSLC B6b2 FSLB B6b1 FSLA B6b0 MHz MHz MHz MHz MHz MHz Spread % 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0.5% Down 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0.5% Down 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0.5% Down 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 1 1 200.00 100.00 33.33 14.318 48.00 96.00 0.5% Down TM TM IDT Programmable Timing Control Hub for Mobile P4 Systems 0930A04/13/10 1 VDDPCIEX GND PCIEXT2 PCICLK5 PCIEXC2 PCICLK4 PCIEXT3 PCICLK3 PCIEXC3 GND SATACLKT VDDPCI SATACLKC PCICLK2/REQ SEL** VDDPCIEX PCI/SRC STOP GND CPU STOP PCIEXC4 REF1/FSLC/TEST SEL PCIEXT4 REF0 PEREQ2 */PCIEXC5 GND PEREQ1 */PCIEXT5 X1 VDDPCIEX X2 ICS954226954226 TM TM Programmable Timing Control Hub for Mobile P4 Systems TSSOP Pin Description PIN PIN NAME TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK3 OUT PCI clock output. 4 PCICLK4 OUT PCI clock output. 5 PCICLK5 OUT PCI clock output. 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI STOP through I2C . ITP EN: latched input to select pin functionality 8 ITP EN/PCICLK F0 I/O 1 = CPU 2 ITP pair 0 = PCIEX 6 pair Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 9 **SELPCIEX LCDCLK /PCICLK F1 I/O Free running 3.3V PCI clock output. Vtt PwrGd is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used 10 Vtt PwrGd /PD IN to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 11 VDD48 PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical 12 FSLA/USB 48MHz I/O characteristics for Vil FS and Vih FS values. / Fixed 48MHz USB clock output. 3.3V. 13 GND PWR Ground pin. 14 DOTT 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC 96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. TEST MODE is a real time 16 FSLB/TEST MODE IN input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK SS output / True clock of PCI Express differential 17 LCDCLK SS/PCIEX0T OUT pair. Selected by SELPCIEX LCDCLK Complementary clock of LCDCLK SS output / Complementary clock of PCI 18 LCDCLK SS/PCIEX0C OUT Express differential pair. Selected by SELPCIEX LCDCLK 19 PCIEXT1 OUT True clock of differential PCI Express pair. 20 PCIEXC1 OUT Complement clock of differential PCI Express pair. 21 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 22 PCIEXT2 OUT True clock of differential PCI Express pair. 23 PCIEXC2 OUT Complement clock of differential PCI Express pair. 24 PCIEXT3 OUT True clock of differential PCI Express pair. 25 PCIEXC3 OUT Complement clock of differential PCI Express pair. 26 SATACLKT OUT True clock of differential SATA pair. 27 SATACLKC OUT Complement clock of differential SATA pair. 28 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V TM TM IDT Programmable Timing Control Hub for Mobile P4 Systems 0930A04/13/10 2