954310 Datasheet Programmable Timing Control Hub for P4 processor Key Specifications: Recommended Application: CPU outputs cycle-cycle jitter < 85ps CK410M Compliant Main Clock PCIEX outputs cycle-cycle jitter < 125ps Output Features: SATA outputs cycle-cycle jitter < 125ps 2 - 0.7V current-mode differential CPU pairs PCI outputs cycle-cycle jitter < 500ps 1 - 0.7V current-mode differential PCIEX/PEREQ +/- 300ppm frequency accuracy on CPU, PCIEX and selectable pair SATA clocks 6 - 0.7V current-mode differential PCIEX pairs +/- 100ppm frequency accuracy on USB clocks 1 - 0.7V current-mode differential CPU ITP/PCIEX Features/Benefits: selectable pairs Supports tight ppm accuracy clocks for Serial-ATA and PCIEX 1 - 0.7V current-mode differential SATA pair Supports programmable spread percentage and 1 - 0.7V current-mode differential frequency LCDCLK/PCIEX/27MHz selectable pair Uses external 14.318MHz crystal, external crystal load 4 - PCI (33MHz) caps are required for frequency tuning 2 - PCICLK F, (33MHz) free-running Supports undriven differential CPU, PCIEX pair in PD 1 - USB, 48MHz for power management. 1 - DOT, 96MHz, 0.7V current differential pair PEREQ pins to support PCIEX power management. 2 - REF, 14.318MHz PWR-SAVE pin for real time power saving. Pin Configuration Functionality Table Pin Configuration CPU PCIEX FSC FSB FS A PCI MHz L L L VDDPCI 1 64 PCICLK2/REQ SEL** MHz MHz Spread % GND 2 63 PCI/PCIEX STOP 00 0 33.33 266.66 100.00 0.5% Down PCICLK3 3 62 CPU STOP 00 1 33.33 133.33 100.00 0.5% Down PCICLK4 4 61 REF1/FSLC/TEST SEL 01 0 33.33 200.00 100.00 0.5% Down *SELPCIEX0 LCD PCICLK5 5 60 REF0 01 1 33.33 166.66 100.00 0.5% Down GND 6 59 GND 10 0 333.33 33.33 100.00 0.5% Down VDDPCI 7 58 X1 10 1 100.00 33.33 100.00 0.5% Down ITP EN/PCICLK F0 8 57 X2 11 0 400.00 33.33 100.00 0.5% Down *SELLCD 27 /PCICLK F1 9 56 VDDREF 11 1 200.00 33.33 100.00 0.5% Down Vtt PwrGd /PD 10 55 SDATA VDD4811 54SCLK FS A/USB 48MHz 12 53 GND L GND 13 52 CPUCLKT0 DOTT 96MHz 14 51 CPUCLKC0 DOTC 96MHz 15 50 VDDCPU FS B/TEST MODE 16 49 CPUCLKT1 L 27FIX/LCD SSCGT/PCIEX0T 17 48 CPUCLKC1 27SS/LCD SSCGC/PCIEX0C 18 47 IREF PCIEXT1 19 46 GNDA PCIEXC120 45VDDA VDDPCIEX 21 44 CPUCLKT2 ITP/PCIEXT8 PCIEXT2 22 43 CPUCLKC2 ITP/PCIEXC8 PCIEXC2 23 42 VDDPCIEX PCIEXT3 24 41 PEREQ1 /PCIEXT7 PCIEXC3 25 40 PEREQ2 /PCIEXC7 SATACLKT 26 39 PCIEXT6 SATACLKC 27 38 PCIEXC6 VDDPCIEX 28 37 GND GND 29 36 PCIEXT5 PCIEXT4 30 35 PCIEXC5 PCIEXC4 31 34 PWRSAVE * *PEREQ3 32 33 PEREQ4 * 64-TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Note: Please add an external resister for pull up or down, never rely on an internal resister when the pin is connected to a device It is not recommended to connect dual function (I/O) pins to slots. 104311/28/05 ICS954310 954310 Datasheet Pin Description PIN PIN NAME TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK3 OUT PCI clock output. 4 PCICLK4 OUT PCI clock output. Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 5 *SELPCIEX0 LCD PCICLK5 I/O 3.3V PCI clock output. 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI STOP . ITP EN: latched input to select pin functionality 8 ITP EN/PCICLK F0 I/O 1 = CPU ITP pair 0 = SRC pair Free running PCI clock not affected by PCI STOP . SELLCD 27 : latched input to select pin functionality 9 *SELLCD 27 /PCICLK F1 I/O 1 = LCDCLK pair 0 = 27MHzSS/27MHzSS pair Vtt PwrGd is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used 10 Vtt PwrGd /PD IN to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 11 VDD48 PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. / Fixed 48MHz USB clock 12 FSLA/USB 48MHz I/O output. 3.3V. 13 GND PWR Ground pin. 14 DOTT 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC 96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. TEST MODE is a real time 16 FSLB/TEST MODE IN input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK output / True clock of PCIEXCLK differential pair/27MHz Non-Spread Push-Pull output, selected by SELPCIEX0 LCD 17 27FIX/LCD SSCGT/PCIEX0T OUT and SELLCD 27 . Complementary clock of LCDCLK SS output / Complementary clock of PCIEXCLK differential pair/27MHz Spreading Push-Pull output, selected by 18 27SS/LCD SSCGC/PCIEX0C OUT SELPCIEX0 LCD and SELLCD 27 . 19 PCIEXT1 OUT True clock of differential PCI Express pair. 20 PCIEXC1 OUT Complement clock of differential PCI Express pair. 21 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 22 PCIEXT2 OUT True clock of differential PCI Express pair. 23 PCIEXC2 OUT Complement clock of differential PCI Express pair. 24 PCIEXT3 OUT True clock of differential PCI Express pair. 25 PCIEXC3 OUT Complement clock of differential PCI Express pair. 26 SATACLKT OUT True clock of differential SATA pair. 27 SATACLKC OUT Complement clock of differential SATA pair. 28 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 29 GND PWR Ground pin. 30 PCIEXT4 OUT True clock of differential PCI Express pair. 31 PCIEXC4 OUT Complement clock of differential PCI Express pair. Real-time input pin that controls PCIEXCLK outputs that are selected 32 *PEREQ3 IN through the I2c. 1 = disabled, 0 = enabled. 104311/28/05 2