DATASHEET Frequency Timing Generator for Peripherals 9FGP205 Pin Configuration Recommended Application: Peripheral Clock for Intel Servers with Wake-On-Lan support Output Features: 1 - 0.7V current-mode differential CPU output 6 - 50MHz RMII outputs 2 - 125MHz RGMII outputs 1 - 0.7V current-mode differential DOT 96MHz output 1 - 33.33MHz output 40 39 38 37 36 35 34 33 32 31 GND130 GNDRMII 1 - 32.768KHz output VDD96229 RMII2 2 - 25MHz REF outputs DOT96SST328 RMII3 DOT96SSC427 GNDRMII OE 96526 VDDRMII Key Specifications: 9FGP205 OE CPU625 RMII4 Exact synthesis on CPU, RGMII, RMII & 33.33MHz CPUCLKT0 RMII5 724 clocks CPUCLKC0823 VDD33 +/- 100ppm frequency accuracy on other clocks VDDCPU922 33.33MHZ/**SMBADR GNDCPU GND33 10 21 11 12 13 14 15 16 17 18 19 20 Features/Benefits: Selectable SMBus Address - D0/D1 or C0/C1 Spread Spectrum capability on CPU and DOT 96MHz clocks 40-MLF SMBus Control: * Internal Pull-Up Resistor - M/N and spread programming on CPU and DOT ** Internal Pull-Dow n Resistor 96MHz clocks via SMBus - Differential outputs can be disabled via pins or SMBus Functionality CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS 33.33 RMII RGMII 25 32.768 MHz MHz MHz MHz MHz MHz KHz Byte0 Bit2 Byte0 Bit1 Byte0 Bit0 0 0 0 266.67 96.00 33.33 50.00 125.00 25.00 32.768 0 0 1 133.33 96.00 33.33 50.00 125.00 25.00 32.768 0 1 0 200.00 96.00 33.33 50.00 125.00 25.00 32.768 0 1 1 166.67 96.00 33.33 50.00 125.00 25.00 32.768 1 0 0 333.33 96.00 33.33 50.00 125.00 25.00 32.768 1 0 1 100.00 96.00 33.33 50.00 125.00 25.00 32.768 1 1 0 400.00 96.00 33.33 50.00 125.00 25.00 32.768 1 1 1 Reserved 96.00 33.33 50.00 125.00 25.00 32.768 Power up default is highlighted. SMBus Address Selection SMBADR SMBADR = 0 SMBADR = 1 D0/D1 C0/C1 IDT Frequency Timing Generator for Peripherals 166407/16/14 1 IREF Vtt PWRGD/WOL STOP VDD32K SMBDAT 32.768KHz SMBCLK GND32K RGMII0 VDDREF RGMII1 25MHz 0 GNDRGMII 25MHZ 1 VDDRGMII GNDREF RMII0 X1 25 RMII1 X2 25 VDDRMII9FGP205 Frequency Timing Generator for Peripherals Pin Description PIN PIN PIN NAME DESCRIPTION TYPE 1 GND PWR Ground pin. 2 VDD96 PWR Power pin for the DOT96 clocks, nominal 3.3V True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are 3 DOT96SST OUT current mode outputs. External resistors are required for voltage bias. Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock. 4 DOT96SSC OUT These are current mode outputs. External resistors are required for voltage bias. Active high input for enabling 96Hz outputs. 5OE 96 IN 1 = enable output(s), 0 = tri-state output(s) Active high input for enabling CPU DIFF pairs. 6OE CPU IN 1 = enable output(s), 0 = tri-state output(s) True clock of differential pair CPU outputs. These are current mode outputs. External resistors 7 CPUCLKT0 OUT are required for voltage bias. Complementary clock of differential pair CPU outputs. These are current mode outputs. 8 CPUCLKC0 OUT External resistors are required for voltage bias. 9 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 10 GNDCPU PWR Ground pin for the CPU outputs This pin establishes the reference current for the differential current-mode output pairs. This pin 11 IREF OUT requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 12 VDD32K PWR Power pin for the 32.768KHz outputs, nominal 3.3V 13 32.768KHz OUT 32.768KHz clock output 14 GND32K PWR Ground pin for the 32.768KHz outputs 15 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 16 25MHz 0 OUT 25MHz clock output, 3.3V 17 25MHZ 1 OUT 25MHz clock output, 3.3V 18 GNDREF PWR Ground pin for the REF outputs. 19 X1 25 IN Crystal input, Nominally 25.00MHz. 20 X2 25 OUT Crystal output, Nominally 25.00MHz. 21 GND33 PWR Ground pin for the 33.33MHz outputs 22 33.33MHZ/**SMBADR I/O 33.33MHz clock output / SMBus address select bit. 23 VDD33 PWR Power pin for the 33.33MHz outputs, nominal 3.3V 24 RMII5 OUT 3.3V 50MHz RMII clock output 25 RMII4 OUT 3.3V 50MHz RMII clock output 26 VDDRMII PWR 3.3V power pin for the RMII clocks. 27 GNDRMII PWR Ground pin for the RMII outputs 28 RMII3 OUT 3.3V 50MHz RMII clock output 29 RMII2 OUT 3.3V 50MHz RMII clock output 30 GNDRMII PWR Ground pin for the RMII outputs 31 VDDRMII PWR 3.3V power pin for the RMII clocks. 32 RMII1 OUT 3.3V 50MHz RMII clock output 33 RMII0 OUT 3.3V 50MHz RMII clock output 34 VDDRGMII PWR 3.3V power pin for the RGMII clocks and PLL 35 GNDRGMII PWR Ground pin for the RGMII outputs 36 RGMII1 OUT 3.3V 125MHz RGMII clock output 37 RGMII0 OUT 3.3V 125MHz RGMII clock output 38 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 39 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant Notifies clock to sample latched inputs on first low to high transition. After first power up, a low 40 CKPWRGD WOL STOP IN stops all outputs except those designated to run in power down mode (WOL STOP mode) IDT Frequency Timing Generator for Peripherals 166407/16/14 2