DATASHEET ICS9LP505-1 64-pin CK505 for Desktop Systems Recommended Application: Key Specifications: CK505 clock, 64-pin Intel Yellow Cover part CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 500ps Output Features: +/- 100ppm frequency accuracy on CPU & SRC clocks 2 - CPU differential low power push-pull pairs 10 - SRC differential low power push-pull pairs 1 - CPU/SRC selectable differential low power push-pull Features/Benefits: pair Supports spread spectrum modulation, default is 0.5% down 1 - SRC/DOT selectable differential low power push-pull spread pair Uses external 14.318MHz crystal, external crystal load caps are 5 - PCI, 33MHz required for frequency tuning 1 - PCI F, 33MHz free running Selectable SRC differential push-pull pair/two single-ended 1 - USB, 48MHz outputs 1 - REF, 14.318MHz Pin Configuration Table 1: CPU Frequency Select Table 2 1 1 PCI0/CR A 1 64 SCLK FS C FS B FS A CPU SRC PCI REF USB DOT L L L VDDPCI 2 63 SDATA MHz MHz MHz MHz MHz MHz B0b7 B0b6 B0b5 PCI1/CR B 3 62 REF0/FSLC/TEST SEL 0 0 0 266.66 PCI2/TME 4 61 VDDREF 0 0 1 133.33 PCI3 5 60 X1 0 1 0 200.00 PCI4/SRC5 EN 6 59 X2 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 PCI F5/ITP EN 7 58 GNDREF 1 0 0 333.33 GNDPCI 8 57 FSLB/TEST MODE 1 0 1 100.00 VDD48 9 56 CK PWRGD/PD 1 1 0 400.00 USB 48MHz/FSLA 10 55 VDDCPU 1 1 1 Reserved GND48 11 54 CPUT0 1. FS A and FS B are low-threshold inputs.Please see V and V specifications in L L IL FS IH FS VDD96 IO 12 53 CPUC0 the Input/Supply/Common Output Parameters Table for correct values. DOTT 96/SRCT0 13 52 GNDCPU Also refer to the Test Clarification Table. DOTC 96/SRCC0 14 51 CPUT1 F 2. FS C is a three-level input. Please see the V and V GND 15 50 CPUC1 F L IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. VDD 16 49 VDDCPU IO SRCT1/SE1 17 48 VOUT SRCC1/SE2 18 47 CPUT2 ITP/SRCT8 GND 19 46 CPUC2 ITP/SRCC8 VDDPLL3 IO 20 45 VDDSRC IO SRCT2/SATAT 21 44 SRCT7/CR F SRCC2/SATAC 22 43 SRCC7/CR E GNDSRC 23 42 GNDSRC SRCT3/CR C 24 41 SRCT6 SRCC3/CR D 25 40 SRCC6 VDDSRC IO 26 39 VDDSRC SRCT4 27 38 PCI STOP /SRCT5 SRCC4 28 37 CPU STOP /SRCC5 GNDSRC 29 36 VDDSRC IO SRCT9 30 35 SRCC10 SRCC9 31 34 SRCT10 SRCC11/CR G 32 33 SRCT11/CR H 64-TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor IDT 64-pin CK505 for Desktop Systems 1112F02/27/09 1 9LP505-1ICS9LP505-1 64-pin CK505 for Desktop Systems Pin Description PIN PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR A EN bit located in byte 5 of SMBUs address space. 1 PCI0/CR A I/O Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR A enabled. Byte 5, bit 6 controls whether CR A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR A controls SRC0 pair (default), 1= CR A controls SRC2 pair 2 VDDPCI PWR Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR B EN bit located in byte 5 of SMBUs address space. 3 PCI1/CR B I/O Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR B enabled. Byte 5, bit 6 controls whether CR B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR B controls SRC1 pair (default) 1= CR B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 4 PCI2/TME I/O 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 5 PCI3 OUT 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI STOP /CPU STOP enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU STOP /PCI STOP is enabled (pins 29 and 30). The latched value controls the pin 6 PCI4/SRC5 EN I/O function on pins 29 and 30 as follows 0 = PCI STOP /CPU STOP 1 = SRC5/SRC5 Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI STOP pin. On powerup, the state of this pin determines whether pins 38 and 7 PCI F5/ITP EN I/O 39 are an ITP or SRC pair. 0 =SRC8/SRC8 1 = ITP/ITP 8 GNDPCI PWR Ground for PCI clocks. 9 VDD48 PWR Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer 10 USB 48MHz/FSLA I/O to input electrical characteristics for Vil FS and Vih FS values. 11 GND48 PWR Ground pin for the 48MHz outputs. 12 VDD96 IO PWR Power supply for DOT96 clocks, nominal 0.8V from source/emitter of external pass transistor. True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 13 DOTT 96/SRCT0 OUT 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0 . After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows 14 DOTC 96/SRCC0 OUT 0= SRC0 1=DOT96 15 GND PWR Ground pin for the DOT96 clocks. 16 VDD PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. IDT 64-pin CK505 for Desktop Systems 1112F02/27/09 2