DATASHEET 56-pin CK505 for Intel Desktop Systems ICS9LP525-2 Recommended Application: Features/Benefits: CK505 clock, 56-pin Intel Yellow Cover part Supports spread spectrum modulation, default is 0.5% down spread Output Features: Uses external 14.318MHz crystal, external crystal load 2 - CPU differential low power push-pull pairs caps are required for frequency tuning 7- SRC differential low power push-pull pairs Selectable SRC differential push-pull pair/two single ended outputs 1 - CPU/SRC selectable differential low power push-pull pair 1 - SRC/DOT selectable differential low power push-pull pair 5 - PCI, 33MHz Table 1: CPU Frequency Select Table 1 - PCI F, 33MHz free running 2 1 1 FS C FS B FS A CPU SRC PCI REF USB DOT L L L 1 - USB, 48MHz MHz MHz MHz MHz MHz MHz B0b7 B0b6 B0b5 1 - REF, 14.318MHz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 Key Specifications: 100.00 33.33 14.318 48.00 96.00 0 1 1 166.66 CPU outputs cycle-cycle jitter < 85ps 1 0 0 333.33 SRC output cycle-cycle jitter < 125ps 1 0 1 100.00 1 1 0 400.00 PCI outputs cycle-cycle jitter < 250ps 1 1 1 Reserved +/- 100ppm frequency accuracy on all outputs 1. FS A and FS B are low-threshold inputs.Please see V and V specifications in L L IL FS IH FS SRC are PCIe Gen2 compliant the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS C is a three-level input. Please see the V and V L IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration PCI0/CR A 1 56 SCLK VDDPCI 2 55 SDATA PCI1/CR B 3 54 REF0/FSLC/TEST SEL PCI2/TME 4 53 VDDREF PCI3/CFG0 5 52 X1 PCI4/SRC5 EN 6 51 X2 PCI F5/ITP EN 7 50 GNDREF GNDPCI 8 49 FSLB/TEST MODE VDD48 9 48 CK PWRGD/PD USB 48MHz/FSLA 10 47 VDDCPU GND48 11 46 CPUT0 VDD96 IO 12 45 CPUC0 DOTT 96/SRCT0 13 44 GNDCPU DOTC 96/SRCC0 14 43 CPUT1 F GND 15 42 CPUC1 F VDD 16 41 VDDCPU IO SRCT1/SE1 17 40 VOUT SRCC1/SE2 18 39 CPUT2 ITP/SRCT8 GND 19 38 CPUC2 ITP/SRCC8 VDDPLL3 IO 20 37 VDDSRC IO SRCT2/SATAT 21 36 SRCT7/CR F SRCC2/SATAC 22 35 SRCC7/CR E GNDSRC 23 34 GNDSRC SRCT3/CR C 24 33 SRCT6 SRCC3/CR D 25 32 SRCC6 VDDSRC IO 26 31 VDDSRC SRCT4 27 30 PCI STOP /SRCT5 SRCC4 28 29 CPU STOP /SRCC5 56-SSOP & TSSOP IDT PC MAIN CLOCK 139711/08/10 1 9LP525-2ICS9LP525-2 PC MAIN CLOCK Pin Description PIN PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRA EN bit located in byte 5 of SMBUs address space. 1 PCI0/CR A I/O Byte 5, bit 7 0 = PCI0 enabled (default) 1= CRA enabled. Byte 5, bit 6 controls whether CRA controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CRA controls SRC0 pair (default), 1= CRA controls SRC2 pair 2 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRB EN bit located in byte 5 of SMBUs address space. 3 PCI1/CR B I/O Byte 5, bit 5 0 = PCI1 enabled (default) 1= CRB enabled. Byte 5, bit 6 controls whether CRB controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CRB controls SRC1 pair (default) 1= CRB controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows 0=Overclocking of CPU and SRC allowed 4 PCI2/TME I/O 1=Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 5 PCI3/CFG0 I/O 3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information 3.3V PCI clock output / SRC5 pair or PCI STOP /CPU STOP enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU STOP /PCI STOP is enabled (pins 29 and 30). The latched value controls the pin function on 6 PCI4/SRC5 EN I/O pins 29 and 30 as follows 0 = PCI STOP /CPU STOP 1 = SRC5/SRC5 Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI STOP pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 7 PCI F5/ITP EN I/O 0 =SRC8/SRC8 1 = ITP/ITP 8 GNDPCI PWR Ground pin for the PCI outputs 9 VDD48 PWR Power pin for the 48MHz output and PLL.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. / Fixed 10 USB 48MHz/FSLA I/O 48MHz USB clock output. 3.3V. 11 GND48 PWR Ground pin for the 48MHz outputs 12 VDD96 IO PWR Power supply for DOT96 clocks, nominal 0.8V from source/emitter of external pass transistor. True clock of low power differential SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 13 DOTT 96/SRCT0 OUT 0= SRC0 1=DOT96 Complement clock of low power differential SRC or DOT96. The power-up default function is SRC0 . After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows 14 DOTC 96/SRCC0 OUT 0= SRC0 1=DOT96 15 GND PWR Ground pin. 16 VDD PWR Power supply, nominal 3.3V True clock of low power differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% 17 SRCT1/SE1 OUT downspread. The pin function may be changed via SMBus B1b 4:1 Complement clock of push-pull differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, - 18 SRCC1/SE2 OUT 0.5% downspread. The pin function may be changed via SMBus B1b 4:1 19 GND PWR Ground pin. 20 VDDPLL3 IO PWR Power supply for PLL3. 0.8V nominal from source/emitter of external pass transistor 21 SRCT2/SATAT OUT True clock of low power differentiall SRC/SATA clock pair. 22 SRCC2/SATAC OUT Complement clock of differential push-pull SRC/SATA clock pair. 23 GNDSRC PWR Ground pin for the SRC outputs TM TM IDT /ICS PC MAIN CLOCK 139711/08/10 2