9LPR363 Datasheet Low Power Programmable Timing Control Hub for P4 processor Key Specifications: Recommended Application: CPU outputs cycle-cycle jitter < 85ps Low Power CK505 Compliant Main Clock PCIEX outputs cycle-cycle jitter < 125ps Output Features: SATA outputs cycle-cycle jitter < 125ps 2 - 0.8V push-pull differential CPU pairs PCI outputs cycle-cycle jitter < 500ps 7 - 0.8V push-pull differential PCIEX pairs +/- 100ppm frequency accuracy on CPU, PCIEX and SATA clocks 1 - 0.8V push-pull differential SATA pair +/- 100ppm frequency accuracy on USB clocks 1 - 0.8V push-pull differential CPU/PCIEX selectable pair 1 - 0.8V push-pull differential 27MHz/LCDCLK/PCIEX selectable pair Features/Benefits: 4 - PCI (33MHz) Supports tight ppm accuracy clocks for Serial-ATA and PCIEX 2 - PCICLK F, (33MHz) free-running Supports programmable spread percentage and 1 - USB, 48MHz frequency 1 - DOT96/PCIEX selectable pair Uses external 14.318MHz crystal, external crystal load 2 - REF, 14.318MHz caps are required for frequency tuning PEREQ pins to support PCIEX power management. Low power differential clock outputs (No 50 resistor to GND needed) iAMT support Pin Configuration Latch Select Table VDDPCI164 PCICLK0/REQ SEL** Pin5 Pin9 Pin14/15 Pin17/18 GND263 PCI/PCIEX STOP PCICLK1362 CPU STOP SELLCD 27 =0 PCIEX9 27FIX/SS SELPCIEX0 LCD / PCICLK2461 REF1/FSLC/TEST SEL PCI3 = 0 (low) SELLCD 27 =1 DOT96 LCD *SELPCIEX0 LCD /PCICLK3560 REF0 659 GND GND SELLCD 27 =0 PCIEX9 PCIEX0 SELPCIEX0 LCD / 758 VDDPCI X1 PCI3 = 1 (high) SELLCD 27 =1 DOT96 PCIEX0 857 ITP EN/PCICLK F4 X2 *SELLCD 27 /PCICLK F5956 VDDREF VttPWR GD/PD 10 55 SDATA Functionality Table VDD48 11 54 SCLK FS A/USB 48MHz 12 53 GND CPU PCIEX L FSC FSB FS A PCI MHz L L L MHz MHz Spread % GND 13 52 CPUT L0 00 0 33.33 PCIeT L9/DOTT 96MHzL 14 51 CPUC L0 266.66 100.00 0.5% Down 15 50 PCIeC L9/DOTC 96MHzL VDDCPU 00 1 133.33 33.33 100.00 0.5% Down FS B/TEST MODE 16 49 CPUT L1F 01 0 L 200.00 33.33 100.00 0.5% Down 17 48 27FIX/LCD SSCGT/PCIeT L0 CPUC L1F 01 1 166.66 33.33 100.00 0.5% Down 27SS/LCD SSCGC/PCIeC L0 18 47 VREF 10 0 33.33 333.33 100.00 0.5% Down PCIeT L1 19 46 GNDA 10 1 100.00 33.33 100.00 0.5% Down PCIeC L1 20 45 VDDA 11 0 400.00 33.33 100.00 0.5% Down VDDPCIEX 21 44 CPUITPT L2/PCIeT L8 11 1 200.00 33.33 100.00 0.5% Down PCIeT L2 22 43 CPUITPC L2/PCIeC L8 PCIeC L2 23 42 VDDPCIEX PCIeT L3 24 41 PEREQ1 /PCIeT L7 25 40 PCIeC L3 PEREQ2 /PCIeC L7 26 39 SATACLKT L PCIeT L6 27 38 SATACLKC L PCIeC L6 VDDPCIEX 28 37 GND GND 29 36 PCIeT L5 30 35 PCIeT L4 PCIeC L5 PCIeC L4 31 34 PWRSAVE * *PEREQ3 32 33 PEREQ4 * 64-TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Note: Please add an external resistor for pull up or down, never rely on an internal resistor when the pin is connected to a device 119908/20/08 ICS9LPR363 9LPR363 Datasheet Pin Description PIN PIN NAME TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK1 OUT PCI clock output. 4 PCICLK2 OUT PCI clock output. 5 *SELPCIEX0 LCD /PCICLK3 N/A N/A 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI STOP . ITP EN: latched input to select CPU ITP/SRC output functionality 8 ITP EN/PCICLK F4 I/O 1 = CPU ITP pair 0 = SRC pair Free running PCI clock not affected by PCI STOP . 9 *SELLCD 27 /PCICLK F5 I/O SELLCD 27 : latched input to select pin functionality. See Latch Select Table This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid 10 VttPWR GD/PD IN and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. 11 VDD48 PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for 12 FSLA/USB 48MHz I/O Vil FS and Vih FS values. / Fixed 48MHz USB clock output. 3.3V. 13 GND PWR Ground pin. True clock of 0.8V differential push-pull PCI Express pair / True clock of differential DOT96 14 PCIeT L9/DOTT 96MHzL OUT output pair. (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI Express pair. / Complement clock of 15 PCIeC L9/DOTC 96MHzL OUT differential DOT96 push-pull output . (no 50ohm resistor to GND needed) 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for 16 FSLB/TEST MODE IN Vil FS and Vih FS values. TEST MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True clock of 17 27FIX/LCD SSCGT/PCIeT L0 OUT low power PCIEXCLK differential pair/ selected by SELPCIEX0 LCD and SELLCD 27 . No 50ohm resistor to GND needed for differential outputs. 27MHz Spreading Push-Pull output / Complementary clock of LCDCLK SS output / 18 27SS/LCD SSCGC/PCIeC L0 OUT Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0 LCD and SELLCD 27 . No 50ohm resistor to GND needed for differential outputs. 19 PCIeT L1 OUT True clock of 0.8V differential push-pull PCI Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI Express pair. (no 50ohm resistor to GND 20 PCIeC L1 OUT needed) 21 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 22 PCIeT L2 OUT True clock of 0.8V differential push-pull PCI Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI Express pair. (no 50ohm resistor to GND 23 PCIeC L2 OUT needed) 24 PCIeT L3 OUT True clock of 0.8V differential push-pull PCI Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI Express pair. (no 50ohm resistor to GND 25 PCIeC L3 OUT needed) 26 SATACLKT L OUT True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed) 27 SATACLKC L OUT Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed) 28 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 29 GND PWR Ground pin. 30 PCIeT L4 OUT True clock of 0.8V differential push-pull PCI Express pair (no 50ohm resistor to GND needed) Complement clock of 0.8V differential push-pull PCI Express pair. (no 50ohm resistor to GND 31 PCIeC L4 OUT needed) Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 = 32 *PEREQ3 IN disabled, 0 = enabled. 119908/20/08 2