Integrated ICS9LPRS365 Circuit Advance Information Systems, Inc. 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor Recommended Application: Pin Configuration CK505 compliant clock with fully integrated voltage regulator PCI0/CR A 1 64 SCLK VDDPCI 2 63 and Internal series resistor on differential outputs SDATA PCI1/CR B 3 62 REF0/FSLC/TEST SEL PCI2/TME 4 61 VDDREF PCI3 5 60 X1 Output Features: PCI4/27 Select659X2 2 - CPU differential low power push-pull pairs PCI F5/ITP EN 7 58 GNDREF 9 - SRC differential low power push-pull pairs GNDPCI 8 57 FSLB/TEST MODE VDD48 9 56 CK PWRGD/PD 1 - CPU/SRC selectable differential low power push-pull pair USB 48MHz/FSLA 10 55 VDDCPU 1 - SRC/DOT selectable differential low power push-pull pair GND4811 54CPUT0 VDD96 IO 12 53 CPUC0 5 - PCI, 33MHz SRCT0/DOTT 96 13 52 GNDCPU 1 - PCI F, 33MHz free running SRCC0/DOTC 96 14 51 CPUT1 F GND 15 50 CPUC1 F 1 - USB, 48MHz VDDPLL3 16 49 VDDCPU IO 1 - REF, 14.318MHz 27MHz NonSS/SRCT1/SE1 17 48 NC 27MHz SS/SRCC1/SE2 18 47 CPUT2 ITP/SRCT8 GND 19 46 CPUC2 ITP/SRCC8 Key Specifications: VDDPLL3 IO 20 45 VDDSRC IO CPU outputs cycle-cycle jitter < 85ps SRCT2/SATAT 21 44 SRCT7/CR F SRCC2/SATAC 22 43 SRCC7/CR E SRC output cycle-cycle jitter < 125ps GNDSRC 23 42 GNDSRC PCI outputs cycle-cycle jitter < 250ps SRCT3/CR C 24 41 SRCT6 SRCC3/CR D 25 40 SRCC6 +/- 100ppm frequency accuracy on CPU & SRC clocks VDDSRC IO 26 39 VDDSRC SRCT427 38PCI STOP SRCC4 28 37 CPU STOP Features/Benefits: GNDSRC 29 36 VDDSRC IO Does not require external pass transistor for voltage SRCT930 35SRCC10 regulator SRCC9 31 34 SRCT10 Integrated 33ohm series resistors on differential outputs, SRCC11/CR G 32 33 SRCT11/CR H Z =50 64-TSSOP o * Internal Pull-Up Resistor Supports spread spectrum modulation, default is 0.5% down ** Internal Pull-Down Resistor spread 64-TSSOP Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning 27 Select (power on latch) 0 1 DOT96, LCD SS SRC0, 27MHz Non SS & SS Pin13/14 & Pin17/18 Selectable between one SRC differential push-pull pair Byte1 bit7 = 1. Byte1 bit7 = 0. and two single-ended outputs Table 1: CPU Frequency Select Table 2 1 1 CPU SRC PCI REF USB FS C FS B FS A DOT L L L MHz MHz MHz MHz MHz MHz B0b7 B0b6 B0b5 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 Reserved 11 1 1. FS A and FS B are low-threshold inputs.Please see V and V specifications in L L IL FS IH FS the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS C is a three-level input. Please see the V and V L IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 121809/09/09 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. 9LPRS365 ICS9LPRS365 Advance Information TSSOP Pin Description PIN PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR A EN bit located in byte 5 of SMBUs address space. 1 PCI0/CR A I/O Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR A enabled. Byte 5, bit 6 controls whether CR A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR A controls SRC0 pair (default), 1= CR A controls SRC2 pair 2 VDDPCI PWR Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR B EN bit located in byte 5 of SMBUs address space. 3 PCI1/CR B I/O Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR B enabled. Byte 5, bit 6 controls whether CR B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR B controls SRC1 pair (default) 1= CR B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 4 PCI2/TME I/O 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 5 PCI3 OUT 3.3V PCI clock output. 3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin 6 PCI4/27 Select I/O determines the power-up default of DOT 96/SRC0 and 27MHz/SRC1 output and the function table for the pin17 and pin18. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI STOP pin. On powerup, the state of this pin determines whether pins 46 and 47 are an ITP or SRC 7 PCI F5/ITP EN I/O pair. 0 =SRC8/SRC8 1 = ITP/ITP 8 GNDPCI PWR Ground for PCI clocks. 9 VDD48 PWR Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input 10 USB 48MHz/FSLA I/O electrical characteristics for Vil FS and Vih FS values. 11 GND48 PWR Ground pin for the 48MHz outputs. 12 VDD96 IO PWR 1.05V to 3.3V from external power supply True clock of SRC or DOT96. The power-up default function depends on 27 Select, 1= SRC0, 13 DOTT 96/SRCT0 OUT 0=DOT96 Complement clock of SRC or DOT96. The power-up default function depends on 27 Select, 1= SRC0, 14 DOTC 96/SRCC0 OUT 0=DOT96 15 GND PWR Ground pin for the DOT96 clocks. 16 VDD PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. 121809/09/09 2