Datasheet PROGRAMMABLE TIMING CONTROL HUB FOR ICS9LRS3187B INTEL BASED SYSTEMS Features/Benefits: Recommended Application: Supports spread spectrum modulation, 0 to -0.5% CK505 version 1.1 clock, with fully integrated voltage regulators down spread for CPU and SRC clocks and series resistors Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Output Features: 2 - CPU differential low power push-pull pairs Available in commercial (0 to +70C) and industrial (-40 to +85C) temperature ranges 1 - SRC differential low power push-pull pair 1 - SATA differential low power push-pull pair Meets PCIe Gen2 specifications 1 - DOT differential low power push-pull pair Key Specifications: 1 - REF, able to drive 3 loads, 14.318MHz CPU outputs cycle-cycle jitter <85ps 1 - 27MHz SS/non SS single-ended output pair SRC outputs cycle-cycle jitter <125ps +/- 100ppm frequency accuracy on all clocks Pin Configuration 32 31 30 29 28 27 26 25 VDDDOT96MHz 3.3 1 24 VDDCPU 3.3 GNDDOT96MHz 2 23 CPUT0 LPR DOT96T LPR 3 22 CPUC0 LPR DOT96C LPR 4 21 GNDCPU 9LRS3187 VDD 27MHz 5 CPUT1 LPR 20 27MHz nonSS 6 CPUC1 LPR 19 27MHz SS 7 VDDCPU IO 18 GND27MHz 8 VDDSRC 3.3 17 9 10111213141516 ** Internal Pull-Down Resistor * Internal Pull-Up Resistor 32-pin MLF IDT Programmable Timing Control Hub for Intel Based Systems 1602F11/04/11 1 GNDSATA SCLK 3.3 SATAT LPR SDATA 3.3 SATAC LPR REF 2L/FSLC 3.3** GNDSRC VDDREF 3.3 SRCT1 LPR X1 SRCC1 LPR X2 VDDSRC IO GNDREF *CPU STOP CLKPWRGD/PD 3.3ICS9LRS3187B Programmable Timing Control Hub for Intel Based Systems Datasheet Pin Description Pin Pin Name Type Pin Description 1 VDDDOT96MHz 3.3 PWR Power pin for the 96MHz output 3.3V. 2 GNDDOT96MHz PWR Ground pin for the 96MHz output True DOT96 output with integrated 33ohm series resistor. No 3 DOT96T LPR OUT 50ohm resistor to GND needed. Complement DOT96 output with integrated 33ohm series 4 DOT96C LPR OUT resistor. No 50ohm resistor to GND needed. 5 VDD 27MHz PWR Power pin for the 27MHz output 3.3V. 6 27MHz nonSS OUT 3.3V Single-ended 27MHz non-spread clock. 7 27MHz SS OUT 3.3V Single-ended 27MHz spread clock. 8 GND27MHz OUT Ground pin for the 27MHz outputs. 9 GNDSATA PWR Ground pin for the SATA outputs. True clock of differential 0.8V push-pull SATA/SRC output with 10 SATAT LPR OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SATA/SRC 11 SATAC LPR OUT output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. 12 GNDSRC PWR Ground pin for the SRC outputs True clock of differential 0.8V push-pull SRC output with 13 SRCT1 LPR OUT integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output 14 SRCC1 LPR OUT with integrated 33ohm series resistor. No 50ohm resistor to GND needed. 15 VDDSRC IO PWR 1.05V to 3.3V from external power supply Stops all CPU clocks, except those set to be free running 16 *CPU STOP IN clocks 17 VDDSRC 3.3 PWR Supply for SRC clocks, 3.3V nominal 18 VDDCPU IO PWR 1.05V to 3.3V from external power supply Complementary clock of differential pair 0.8V push-pull CPU 19 CPUC1 LPR OUT outputs with integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with 20 CPUT1 LPR OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. 21 GNDCPU PWR Ground pin for the CPU outputs. Complementary clock of differential pair 0.8V push-pull CPU 22 CPUC0 LPR OUT outputs with integrated 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with 23 CPUT0 LPR OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. 24 VDDCPU 3.3 PWR Supply for CPU clocks, 3.3V nominal 25 CLKPWRGD/PD 3.3 IN Notifies CK505 to sample latched inputs, or PWRDWN mode 26 GNDREF PWR Ground pin for the REF outputs. 27 X2 OUT Crystal output, Nominally 14.318MHz 28 X1 IN Crystal input, Nominally 14.318MHz 29 VDDREF 3.3 PWR Power pin for the XTAL and REF clocks, nominal 3.3V 14.318 MHz reference clock, which can drive 2 loads / 3.3V 30 REF 2/FSLC 3.3** I/O tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. 31 SDATA 3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant 32 SCLK 3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. IDT Programmable Timing Control Hub for Intel Based Systems 1602F11/04/11 2