DATASHEET PC MAIN CLOCK ICS9UMS9610 Features/Benefits: Recommended Application: Supports Dothan ULV CPUs with 100 to 200 MHz Poulsbo Based Ultra-Mobile PC (UMPC) - CK610 CPU outputs Output Features: Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins 3 - CPU low power differential push-pull pairss CPU STOP input for power manangment 3 - SRC low power differential push-pull pairs Fully integrated Vreg 1 - LCD100 SSCD low power differential push-pull pair Integrated series resistors on differential outputs 1 - DOT96 low power differential push-pull pair 1.5V VDD IO, 1.5V VDD core, 3.3V VDD supply pin for 1 - REF, 14.31818MHz, 3.3V SE output REF Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 CPU STOP 3.3 1 36 *CR 2 1.5 CLKPWRGD /PD 3.3 2 35 SRCT2 LPR X2 3 34 SRCC2 LPR X1 4 33 GNDSRC VDDREF 3.3 5 32 SRCT1 LPR REF 3.3 2x 6 31 SRCC1 LPR 9UMS9610 GNDREF 7 30 VDDIO 1.5 VDDCORE 1.5 8 29 VDDCORE 1.5 FSC L 1.5 9 28 *CR 1 1.5 TEST MODE 1.5 10 27 SRCT0 LPR TEST SEL 1.5 11 26 SRCC0 LPR SCLK 3.3 12 25 GNDSRC 13 14 15 16 17 18 19 20 21 22 23 24 48-pin MLF, 6x6 mm, 0.4mm pitch * indicates inputs with internal pull up of ~10Kohm to 1.5V TM M IDT /ICST PC MAIN CLOCK 133606/01/09 1 SDATA 3.3 CPUT0 LPR VDDCORE 1.5 CPUC0 LPR VDDIO 1.5 VDDIO 1.5 DOT96C LPR GNDCPU DOT96T LPR CPUT1 LPR GNDDOT CPUC1 LPR GNDLCD VDDCORE 1.5 LCD100C LPR VDDIO 1.5 LCD100T LPR GNDCPU VDDIO 1.5 CPUT2 LPR VDDCORE 1.5 CPUC2 LPR *CR 0 1.5 FSB L 1.5ICS9UMS9610 PC MAIN CLOCK Pin Description Logic Level Input Level PIN PIN NAME TYPE DESCRIPTION (V) Tolerance (V) 1 CPU STOP 3.3 IN This active-low input stops all CPU clocks that are set to be stoppable. 3.3 3.3 This level sensitive strobe determines when latch inputs are valid and are 2 CLKPWRGD /PD 3.3 IN ready to be sampled. When high, this asynchronous input places the 3.3 3.3 device into the power down state. 3 X2 OUT Crystal output, Nominally 14.318MHz N/A N/A 4 X1 IN Crystal input, Nominally 14.318MHz. 1.5 1.5 5 VDDREF 3.3 PWR Power pin for the XTAL and REF clocks, nominal 3.3V 3.3 3.3 6 REF 3.3 2x OUT 3.3V 14.318 MHz reference clock. Default 2 load drive strength 3.3 N/A 7 GNDREF GND Ground pin for the REF outputs. 0 N/A 8 VDDCORE 1.5 PWR 1.5V power for the PLL core 1.5 1.5 Low threshold input for CPU frequency selection. Refer to input electrical 9 FSC L 1.5 IN 1.5 1.5 characteristics for Vil FS and Vih FS values. 1.5V Max input voltage. TEST MODE is a real time input to select between Hi-Z and REF/N divider 10 TEST MODE 1.5 IN mode while in test mode. Refer to Test Clarification Table. Max input 1.5 3.3 voltage is 1.5V. TEST SEL: latched input to select TEST MODE. Max input voltage is 1.5V 11 TEST SEL 1.5 IN 1 = All outputs are tri-stated for test 1.5 3.3 0 = All outputs behave normally. 12 SCLK 3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 3.3 3.3 13 SDATA 3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 3.3 3.3 14 VDDCORE 1.5 PWR 1.5V power for the PLL core 1.5 1.5 15 VDDIO 1.5 PWR Power supply for low power differential outputs, nominal 1.5V. 1.5 1.5 Complement clock of low power differential pair for 96.00MHz DOT clock. 16 DOT96C LPR OUT 0.8 N/A No 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for 96.00MHz DOT clock. No 17 DOT96T LPR OUT 0.8 N/A 50ohm resistor to GND needed. No Rs needed. 18 GNDDOT GND Ground pin for DOT clock output 0 N/A 19 GNDLCD GND Ground pin for LCD clock output 0 N/A Complement clock of low power differential pair for LCD100 SS clock. No 20 LCD100C LPR OUT 0.8 N/A 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for LCD100 SS clock. No 50ohm 21 LCD100T LPR OUT 0.8 N/A resistor to GND needed. No Rs needed. 22 VDDIO 1.5 PWR Power supply for low power differential outputs, nominal 1.5V. 1.5 1.5 23 VDDCORE 1.5 PWR 1.5V power for the PLL core 1.5 1.5 24 *CR 0 1.5 IN 1.5V Clock request for SRC0, 0 = enable, 1 = disable 1.5 1.5 TM M IDT /ICST PC MAIN CLOCK 133606/01/09 2