DATASHEET VERY LOW POWER CLOCK FOR 2011 NETBOOKS 9VRS4339B General Description Features/Benefits The 9VRS4339B is a Intel CK-NET compatible main clock Supports Wake On LAN (see pin55 pin description) for Intel Netbooks, conforming to the CK-NET specification. Selectable spread % on CPU, SRC, PCI Supports It is driven with a 25MHz crystal and generates a variety of margining clocks, including an LCD clock. An SMBus interface allows Uses external 25MHz crystal, external crystal load caps full control of the device. are required for frequency tuning CLKREQ pins Support SRC power management Output Features Low power differential clock outputs driving 100 ohm 2 0.8V push-pull differential CPU pairs differential traces reduced powe 5 0.8V push-pull differential SRC pairs Integrated 33 ohm series resistors on all differential 1 0.8V push-pull differential SATA pair outputs reduced board space 1 0.8V push-pull differential DOT96/SRC pair Key Specifications 1 0.8V push-pull differential LCD100 pair 1 0.8V push-pull differential CPU ITP/SRC pair CPU outputs cycle-to-cycle jitter <85ps 2 PCI (33MHz) SRC cycle-to-cycle jitter <85ps 1 PCI F, (33MHz) free-running SRC meets PCIEX Gen2 specifications 1 USB 48MHz SATA outputs cycle-to-cycle jitter <125ps 1 48MHz PCI outputs cycle-to-cycle jitter <500ps 1 25MHz 100ppm frequency accuracy on all clocks 1 27MHz/PCI 1 14.318MHz Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 SRC2 LPRS X2142 SRC2 LPRS X1241 VDD25 3.3340 GNDSRC SRC6 LPRS 25M 4 39 SDATA 3.3 5 38 SRC6 LPRS SCLK 3.3 6 37 SRC3 LPRS VDDPCI 3.3 7 36 SRC3 LPRS 9VRS4339B vITP EN/PCI F1 2x 8 35 PCI STOP 3.3 VDDSRC LVIO FSLB/PCI2 2x 9 34 10 SRC4 LPRS CLKREQA /PCI3 2x 33 SRC4 LPRS GNDPCI 11 32 SATA LPRS GND14M 12 31 SATA LPRS 14M 2X/FSLC 13 30 VDD14 3.3 14 29 GNDSATA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v prefix indicates internal pull-down resistor prefix indicates internal pull-up resistor IDT VERY LOW POWER CLOCK FOR 2011 NETBOOKS 1 9VRS4339B REV A 010312 VDD48 3.3 GND25 DOT96 SEL/USB48M CLKPWRGD/PD 3.3 CLKREQC /48M CPU0 LPRS GND48 CPU0 LPRS CLKREQB GNDCPU VDD27 CPU1 LPRS vSEL PCI/27M PCI4 2X CPU1 LPRS GND27 VDDCPU LVIO DOT96 LPRS/SRC5 LPRS VDD CORE 1.5 DOT96 LPRS/SRC5 LPRS CPU ITP/SRC1 LPRS VDD CORE 1.5 CPU ITP /SRC1 LPRS LCD100 LPRS CPU STOP 3.3 LCD100 LPRS SRC7 LPRS GNDLCD SRC 7 LPRS9VRS4339B VERY LOW POWER CLOCK FOR 2011 NETBOOKS Pin Descriptions PIN PIN NAME TYPE DESCRIPTION 1 X2 OUT Crystal output, nominally 25MHz 2X1 IN Crystal input, nominally 25MHz 3 VDD25 3.3 PWR Power pin for crystal and 25MHz output, nominal 3.3V 4 25M OUT 3.3V 25MHz clock output 5 SDATA 3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 6 SCLK 3.3 OUT Clock pin of SMBus circuitry, 3.3V tolerant. 7 VDDPCI 3.3 PWR Power supply for PCI clocks, nominal 3.3V ITP enable latched input ITP Enable Selects the functionality of the CPU ITP/SRC output as follows: 8 vITP EN/PCI F1 2x I/O 1 = CPU ITP output 0 = SRC1 output / Free-Running 3.3V PCI clock output, default to drive 2 loads. 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see 9 FSLB/PCI2 2x I/O input electrical characteristics for Vil FS and Vih FS values / 3.3V PCI clock output, default to drive 2 loads. 3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. Pin function is programmable through SMBus. See CLKREQ Control Table and SRC Power Management Table for details 10 CLKREQA /PCI3 2x I/O 0 = controlled outputs are enabled 1 = controlled outputs are Low/Low / 3.3V PCI clock output, default to drive 2 loads 11 GNDPCI PWR Ground pin for the PCI outputs 12 GND14M PWR Ground pin for the 14.318MHz output 3.3V 14.318 MHz clock output, default to drive 2 loads / 3.3V tolerant input for CPU 13 14M 2X/FSLC I/O frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. 14 VDD14 3.3 PWR Power pin for 14.318MHz output, nominal 3.3V 15 VDD48 3.3 PWR Power pin for 48MHz outputs, nominal 3.3V Input latched pin to select Pin23/24 as DOT 96MHz clock or SRC clock 1 = DOT96 output 16 DOT96 SEL/USB48M I/O 0 = SRC5 output / 3.3V 48MHz USB clock output. 3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. Pin function is programmable through SMBus. See CLKREQ Control Table and SRC Power Management Table for details 17 CLKREQC /48M I/O 0 = controlled outputs are enabled 1 = controlled outputs are Low/Low / 3.3V 48MHz clock output 18 GND48 PWR Ground pin for 48MHz outputs 3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 19 CLKREQB IN 0 = controlled outputs are enabled 1 = controlled outputs are Low/Low 20 VDD27 PWR Power pin for 27MHz output , nominal 3.3V 3.3V input latch pin to select this pin as 27M output or PCI4 clock output. This pin has an internal pulldown resistor. Latch functionality is as follows: 21 vSEL PCI/27M PCI4 2X I/O 0 = 27MHz output 1 = 33.33MHz PCI output 22 GND27 PWR Ground pin for the 27MHz output True clock of push-pull DOT96 or SRC clock with integrated series resistor. No 50 23 DOT96 LPRS/SRC5 LPRS OUT ohm pull down needed. Default is pending on Pin16 DOT96 SEL. Complement clock of push-pull DOT96 or SRC clock with integrated series resistor. 24 DOT96 LPRS/SRC5 LPRS OUT No 50 ohm pull down needed. Default is pending on Pin16 DOT96 SEL. 25 VDD CORE 1.5 PWR Power pin for core PLL s, nominal 1.5V. True clock of differential push-pull LCD100 output with integrated 33ohm series 26 LCD100 LPRS OUT resistor. No 50ohm resistor to GND needed. Complementary clock of differential push-pull LCD100 output with integrated 33ohm 27 LCD100 LPRS OUT series resistor. No 50ohm resistor to GND needed. 28 GNDLCD PWR Ground pin for LCD clock output IDT VERY LOW POWER CLOCK FOR 2011 NETBOOKS 2 9VRS4339B REV A 010312