9UMS9633BFILF Renesas

Datasheet ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE ICS9UMS9633BW Recommended Application: Features/Benefits: AEC Q100 compliant Poulsbo Based Ultra-Mobile PC (UMPC) for Automotive Use Supports ULV CPUs with 67 to 167 MHz Output Features: CPU outputs Dedicated TEST/SEL and TEST/MODE pins 3 - CPU low power differential push-pull pairs saves isolation resistors on pins 3 - SRC low power differential push-pull pairs CPU STOP input for power manangment 1 - LCD100 SSCD low power differential Fully integrated Vreg push-pull pair Integrated series resistors on differential 1 - DOT96 low power differential push-pull outputs pair 1.5V VDD IO operation, 3.3V VDD core and 1 - REF, 14.31818MHz, 3.3V SE output REF supply pin for REF -40 to +85C operating range SSOP Pin Configuration REF 1 48 VDDREF 3.3 GNDREF X1 247 VDDCORE 3.3 X2 346 FSC L CLKPWRGD /PD 3.3 445 TEST MODE CPU STOP 544 TEST SEL CPUT0 LPR 643 SCLK CPUC0 LPR 742 VDDIO 1.5 SDATA 8 41 VDDCORE 3.3 GNDCPU 940 VDDIO 1.5 CPUT1 LPR 10 39 DOT96C LPR CPUC1 LPR 11 38 DOT96T LPR VDDCORE 3.3 12 37 GNDDOT 13 36 VDDIO 1.5 GNDLCD 14 GNDCPU 35 LCD100C LPR 15 CPUT2 LPR 34 LCD100T LPR 16 CPUC2 LPR 33 VDDIO 1.5 17 FSB L 32 VDDCORE 3.3 18 *CR 2 31 *CR 0 19 SRCT2 LPR 30 GNDSRC 20 SRCC2 LPR 29 SRCC0 LPR 21 GNDSRC 28 SRCT0 LPR 22 SRCT1 LPR 27 *CR 1 23 SRCC1 LPR 26 VDDCORE 3.3 24 VDDIO 1.5 25 48 SSOP Package * indicates inputs with internal pull up of ~10Kohm to 3.3V TM TM IDT /ICS Ultra Mobile PC Clock for Automotive use 1425A09/02/09 1 9UMS9633ICS9UMS9633BW Datasheet ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE SSOP Pin Description PIN PIN NAME TYPE DESCRIPTION 1 REF OUT 14.318 MHz reference clock. 2 GNDREF PWR Ground pin for the REF outputs. 3 VDDCORE 3.3 PWR 3.3V power for the PLL core Low threshold input for CPU frequency selection. Refer to input electrical 4FSC L IN characteristics for Vil FS and Vih FS values. TEST MODE is a real time input to select between Hi-Z and REF/N divider mode 5 TEST MODE IN while in test mode. Refer to Test Clarification Table. TEST SEL: latched input to select TEST MODE 6 TEST SEL IN 1 = All outputs are tri-stated for test 0 = All outputs behave normally. 7 SCLK IN Clock pin of SMBus circuitry, 5V tolerant. 8 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant. 9 VDDCORE 3.3 PWR 3.3V power for the PLL core 10 VDDIO 1.5 PWR Power supply for low power differential outputs, nominal 1.5V. Complementary clock of low power differential pair for 96.00MHz DOT clock. No 11 DOT96C LPR OUT 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor 12 DOT96T LPR OUT to GND needed. No Rs needed. 13 GNDDOT PWR Ground pin for DOT clock output 14 GNDLCD PWR Ground pin for LCD clock output Complementary clock of low power differential pair for LCD100 SS clock. No 50ohm 15 LCD100C LPR OUT resistor to GND needed. No Rs needed. True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to 16 LCD100T LPR OUT GND needed. No Rs needed. 17 VDDIO 1.5 PWR Power supply for low power differential outputs, nominal 1.5V. 18 VDDCORE 3.3 PWR 3.3V power for the PLL core 19 *CR 0 IN Clock request for SRC0, 0 = enable, 1 = disable 20 GNDSRC PWR Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm 21 SRCC0 LPR OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series 22 SRCT0 LPR OUT resistor. No 50ohm resistor to GND needed. 23 *CR 1 IN Clock request for SRC1, 0 = enable, 1 = disable 24 VDDCORE 3.3 PWR 3.3V power for the PLL core TM TM IDT /ICS Ultra Mobile PC Clock for Automotive use 1425A09/02/09 2