DATASHEET VERY LOW POWER CLOCK FOR 2011 NETBOOKS 9VRS4338D General Description Features/Benefits The 9VRS4338D is a main clock for Intel Netbooks, 25M output can run in power down Supports conforming to the CK-NET specification. It is driven with a Wake On LAN 14.31818MHz crystal and generates a variety of clocks, Selectable spread % on CPU, SRC, PCI Supports including an LCD clock. An SMBus interface allows full margining control of the device. External 14.318MHz crystal Supports tight ppm Recommended Application CLKREQ pins Support SRC power management Low power differential clock outputs reduced power and CK-NET board space Output Features Integrated 33 ohm series resistors on all differential outputs reduced board space 2 - 0.8V push-pull differential CPU pairs 3 - 0.8V push-pull differential SRC pairs Key Specifications 1 - 0.8V push-pull differential SATA/SRC pair CPU cycle-to-cycle jitter <85ps 1 - 0.8V push-pull differential DOT96/SRC pair SRC/SATA cycle-to-cycle jitter <85ps 1 - 0.8V push-pull differential LCD100 pair SRC(1:4) are PCIe Gen2 compliant 1 - 0.8V push-pull differential CPU ITP/SRC pair SRC5 is PCIe Gen1 compliant 3 - PCI (33MHz), 1 free-running 100ppm frequency accuracy on all clocks except 25M 1 - 25MHz PCI (33MHz) 30ppm frequency accuracy on 25M 1 - USB 48MHz 1 - REF, 14.318MHz Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 X2 36 1 SRC2 LRS X1 2 35 SRC2 LRS VDDREF 3 34 GNDSRC REF0 2x/FSLC 4 33 SRC3 LRS SDATA 3.3 32 5 SRC3 LRS SCLK 3.3 31 6 PCI STOP 3.3 9VRS4338D VDDPCI 3.3 7 30 VDDSRC LVIO vITP EN/PCI F1 2x 8 29 SRC4 LRS FSLB/PCI2 2x 9 28 SRC4 LRS CLKREQA /PCI3 2x 10 27 SATA LRS GNDPCI 11 26 SATA LRS GND25 12 25 GNDSATA 13 14 15 16 17 18 19 20 21 22 23 24 48-pin MLF, 6x6 mm, 0.4mm pitch v prefix indicates internal 120KOhm pull down resistor prefix indicates internal 120KOhm pull up resistor IDT VERY LOW POWER CLOCK FOR 2011 NETBOOKS 1 9VRS4338D REV A 022616 vSEL PCI/25M PCI4 2x GNDREF VDD25 CLKPWRGD/PD 3.3 VDD48 CPU0 LRS vUSB 48Mhz 2x CPU0 LRS GND48 GNDCPU CLKREQB CPU1 LRS DOT96 LRS/SRC5 LRS CPU1 LRS DOT96 LRS/SRC5 LRS VDDCPU LVIO VDD CORE 1.5 VDD CORE 1.5 LCD100 LRS CPU ITP/SRC1 LRS LCD100 LRS CPU ITP /SRC1 LRS GNDLCD CPU STOP 3.39VRS4338D VERY LOW POWER CLOCK FOR 2011 NETBOOKS Pin Descriptions PIN PIN NAME TYPE DESCRIPTION 1X2 OUTCrystal output, Nominally 14.318MHz 2 X1 IN Crystal input, Nominally 14.318MHz. 3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 2x strength 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency 4 REF0 2x/FSLC I/O selection. Refer to input electrical characteristics for Vil FS and Vih FS values. 5 SDATA 3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 6SCLK 3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 7VDDPCI 3.3 PWR Power supply for PCI clocks, nominal 3.3V ITP Enable Latched Input/Free Running PCI clock output. ITP Enable Selects the functionality of the CPU ITP/SRC output as follows: 8 vITP EN/PCI F1 2x I/O 1 = CPU ITP output 0 = SRC output 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, 9 FSLB/PCI2 2x I/O see input electrical characteristics for Vil FS and Vih FS values. / 3.3V PCI clock output. Active low realtime input pin to enable SRC Outputs / PCI clock output. (pin 10 CLKREQA /PCI3 2x I/O function is programmable through SMBus). See CLKREQ Control Table and SRC Power Management Table for details. 11 GNDPCI PWR Ground pin for the PCI outputs GND25 12 PWR Ground pin for the 25MHz outputs SEL PCI 3.3V latched input to select pin functionality for 25M PCICLK3 output/25M or PCI clock output. This pin has an internal 120Kohm pulldown 13 vSEL PCI/25M PCI4 2x I/O resistor. Latch functionality is as follows: 0 = 25MHz output 1 = 33.3MHz PCICLK 14 VDD25 PWR Power pin for the 25MHz output.3.3V VDD48 15 PWR Power pin for the 48MHz output.3.3V 3.3V 48MHz USB clock output. This pin has an internal 120Kohm pull down 16 vUSB 48Mhz 2x OUT resistor. 17 GND48 PWR Ground pin for the 48MHz outputs Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 18 CLKREQB IN 0 = controlled outputs are enabled 1 = controlled outputs are Low/Low True clock of push-pull DOT96 or SRC clock with integrated series resistor. No 19 DOT96 LRS/SRC5 LRS OUT 50 ohm pull down needed. Default is DOT96. After powerup, this pin function may be changed to SRC via SMBus. Complementary clock of push-pull DOT96 or SRC clock with integrated series 20 DOT96 LRS/SRC5 LRS OUT resistor. No 50 ohm pull down needed. Default is DOT96. After powerup, this pin function may be changed to SRC via SMBus. 21 VDD CORE 1.5 PWR Power for PLL c ore components requiring 1.5V True clock of differential push-pull LCD100 output with integrated 33ohm series 22 LCD100 LRS OUT resistor. No 50ohm resistor to GND needed. Complementary clock of differential push-pull LCD100 output with integrated 23 LCD100 LRS OUT 33ohm series resistor. No 50ohm resistor to GND needed. 24 GNDLCD PWR Ground pin for LCD clock output IDT VERY LOW POWER CLOCK FOR 2011 NETBOOKS 2 9VRS4338D REV A 022616