F1958EVS Renesas

7-Bit 0.25dB Digital Step Attenuator F1958 1MHz to 6GHz Datasheet Description Features TM The F1958 is part of IDTs Glitch-Free family of DSAs optimized Serial and 7-bit parallel interface for the demanding requirements of Base Station (BTS) radio cards 31.75dB range and numerous other applications. This device is offered in a 0.25dB steps compact 4mm x 4mm 24-pin package with 50 input and output TM Glitch-Free : low transient overshoot impedance for ease of integration into the radio or RF system. 500ns settling time for 0.25dB steps The F1958 offers very high reliability due to its construction from a Ultra linear > 63dBm IIP3 monolithic silicon die in a QFN package. The insertion loss is very Low insertion loss < 1.7dB at 4GHz low with minimal distortion. Additionally, the device is designed to have extremely accurate attenuation levels. These accurate Attenuation error < 0.2dB at 4GHz attenuation levels improve system SNR and/or ACLR by ensuring Bi-directional RF use system gain is as close to the targeted level as possible. In addition, 3.3V or 5V supply the very fast settling time in parallel mode is ideal for fast switching TM -40C to +105C operating temperature systems. Finally, the device uses our Glitch-Free technology in contrast to competing DSAs. 4mm x 4mm Thin QFN 24-pin package Block Diagram Competitive Advantage Figure 1. Block Diagram Lowest insertion loss for best SNR TM Glitch-Free technology to protect power amplifiers or ADC during transitions between attenuation states TM Extremely accurate attenuation levels Glitch-Free Ultra-low distortion MSL1 and 2000 V HBM ESD RF2 RF1 Typical Applications SPI Decoder Bias 3G/4G/4G+ Base Station Systems Distributed Antenna Systems, DAS Remote Radio Heads Active Antenna Systems, AAS Broadband Satellite Equipment NFC Infrastructure Military Communication Equipment 2019 Integrated Device Technology, Inc. 1 November 13, 2019 V DD V MODE D 6:0 DATA CLK LEF1958 Datasheet Pin Assignments Figure 2. Pin Assignments for 4mm x 4mm x 0.75mm TQFN Package Top View 1 18 D0 DATA 2 Decoder SPI 17 CLK VDD B I A S 3 16 LE VMODE 4 15 GND GND RF1 5 14 RF2 GND 6 13 GND EPAD Pin Descriptions Table 1. Pin Descriptions Number Name Description 1 D0 Parallel control pin 0.25dB. Pull high for attenuation. 2 V Power supply input. Bypass to ground with capacitors as close as possible to pin. DD Parallel or serial programming mode pin. Leave open or logic LOW for parallel mode. Logic HIGH for 3 V MODE serial mode. 4, 6 - 13, 15 GND Internally grounded. These pins must be grounded as close to the device as possible. RF Port 1. Can be used as either the input or output RF (bi-directional). Port must be at 0V DC. An 5 RF1 external AC coupling capacitor must be used if there is a DC voltage present. RF Port 2. Can be used as either the input or output RF (bi-directional). Port must be at 0V DC. An 14 RF2 external AC coupling capacitor must be used if there is a DC voltage present. 16 LE Serial latch enable. 17 CLK Serial clock input. 18 DATA Serial data input. a 19 D6 Parallel control pin 16dB. Pull HIGH for attenuation. a 20 D5 Parallel control pin 8dB. Pull HIGH for attenuation. a 21 D4 Parallel control pin 4dB. Pull HIGH for attenuation. a 22 D3 Parallel control pin 2dB. Pull HIGH for attenuation. a 23 D2 Parallel control pin 1dB. Pull HIGH for attenuation. a 24 D1 Parallel control pin 0.5dB. Pull HIGH for attenuation. Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board EPAD (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance. a There is a 500k pull-down resistor to ground. 2019 Integrated Device Technology, Inc. 2 November 13, 2019 GND 7 24 D1 GND 8 23 D2 GND 9 22 D3 GND 10 21 D4 GND 11 20 D5 GND 12 19 D6