DATASHEET PLL BUILDING BLOCK ICS673-01 Description Features The ICS673-01 is a low cost, high-performance Phase Packaged in 16-pin SOIC Locked Loop (PLL) designed for clock synthesis and Available in RoHS compliant package synchronization. Included on the chip are the phase Access to VCO input and feedback paths of PLL detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide Output operating range up to 120 MHz (5 V) by two of the other. Through the use of external reference Able to lock MHz range outputs to kHz range inputs and VCO dividers (the ICS674-01), the user can customize through the use of external dividers the clock to lock to a wide variety of input frequencies. Output Enable tri-states outputs The ICS673-01 also has an output enable function that puts Low skew output clocks both outputs into a high-impedance state. The chip also has Power-down turns off chip a power-down feature which turns off the entire device. VCO predivide to feedback divider of 1 or 4 For applications that require low jitter or jitter attenuation, see the MK2069. 25 mA output drive capability at TTL levels Advanced, low power, sub-micron CMOS process Single supply +3.3 V (5%) or +5 V (10%) operating voltage Industrial and commercial temperature ranges Forms a complete PLL, using the ICS674-01 For better jitter performance, use the MK1575 Block Diagram CHCP VCOIN VDD 2 VDD I cp REFIN UP CLK1 Clock Input Phase/ 1 2 Frequency VCO MUX 2 CLK2 FBIN DOWN Detector 0 4 I cp PD (entire chip) 3 CAP SEL OE (both GND outputs) External Feedback Divider (such as the ICS674-01) IDT / ICS PLL BUILDING BLOCK 1 ICS673-01 REV Q 071906ICS673-01 PLL BUILDING BLOCK PLL BUILDING BLOCK VCO Predivide Select Table Pin Assignment SEL VCO Predivide FBIN 1 16 REFIN 04 VDD 2 15 NC 11 VDD 3 14 CLK1 0 = connect pin directly to ground GND 4 13 CLK2 1 = connect pin directly to VDD GND 5 12 PD GND 6 11 SEL CHGP 7 10 OE VCOIN 8 9 CAP 16 pin narrow (150 m il) SO IC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 FBIN Input Feedback clock input. Connect the feedback clock to this pin. Triggered on falling edge. 2 VDD Power Connect to +3.3 V or +5 V and to VDD on pin 3. 3 VDD Power Connect to VDD on pin 2. 4 GND Power Connect to ground. 5 GND Power Connect to ground. 6 GND Power Connect to ground. 7 CHGP Output Charge pump output. Connect to VCOIN under normal operation. 8 VCOIN Input Input to internal VCO. 9 CAP Input Loop filter return. 10 OE Input Output enable. Active when high. Tri-states both outputs when low. Internal weak pull-up resistor. 11 SEL Input Select pin for VCO predivide to feedback divider per table above. Internal weak pull-up resistor. 12 PD Input Power down. Turns off entire chip when pin is low. Outputs stop low. Internal weak pull-up resistor. 13 CLK2 Output Clock output 2. Low skew divide by two version of CLK1. 14 CLK1 Output Clock output 1. 15 NC - No connect. Nothing is connected internally to this pin. 16 REFIN Input Reference input. Connect reference clock to this pin. Triggered on falling edge. IDT / ICS PLL BUILDING BLOCK 2 ICS673-01 REV Q 071906