ICS87931BYILF Renesas

GND GND QA1 QC1 QA0 QC0 VDDO VDDO DIV SELA EXT FB DIV SELB CLK EN1 DIV SELC CLK EN0 nc nc Low Skew, 1-to-6, LVCMOS/LVTTL Clock ICS87931I Multiplier/Zero Delay Buffer GENERAL DESCRIPTION FEATURES Fully integrated PLL The ICS87931I is a low voltage, low skew LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer. With output frequencies up to 150MHz, Six LVCMOS/LVTTL outputs, 7 typical output impedance the ICS87931I is targeted for high performance clock applica- Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL tions. Along with a fully integrated PLL, the ICS87931I contains clock for redundant clock applications frequency configurable outputs and an external feedback input Maximum output frequency: 150MHz for regenerating clocks with zero delay. VCO range: 220MHz to 480MHz Selectable clock inputs, CLK1 and differential CLK0, nCLK0 sup- port redundant clock applications. The CLK SEL input determines External feedback for zero delay clock regeneration which reference clock is used. The output divider values of Bank Output skew, Same Frequency: 300ps (maximum) A, B and C are controlled by the DIV SELA, DIV SELB and Output skew, Different Frequency: 400ps (maximum) DIV SELC, respectively. Cycle-to-cycle jitter: 100ps (maximum) For test and system debug purposes, the PLL SEL input allows the PLL to be bypassed. When LOW, the nMR input resets the 3.3V supply voltage internal dividers and forces the outputs to the high impedance -40C to 85C ambient operating temperature state. The effective fanout of the ICS87931I can be increased to 12 by utilizing the ability of each output to drive two series terminated PIN ASSIGNMENT transmission lines. 32 31 30 29 28 27 26 25 nc 1 24 GND VDDA 2 23 QB0 ICS87931I POWER DN 3 22 QB1 32-Lead LQFP CLK1 4 21 VDDO 7mm x 7mm x 1.4mm nMR 5 20 EXTFB SEL package body CLK0 6 19 CLK SEL Y package nCLK0 7 18 PLL SEL Top View GND 8 17 nc BLOCK DIAGRAM 9 10 11 12 13 14 15 16 Pullup POWER DN Pullup PLL SEL Pulldown CLK SEL Pullup CLK1 0 Pullup 1 CLK0 0 QA0 2/4 PHASE 1 0 VCO None DETECTOR 2 nCLK0 1 QA1 Pulldown LPF EXTFB SEL Pullup EXT FB 1 2/4 QB0 8 0 QB1 DIV SELA Pulldown Pulldown DIV SELB Pullup 4/6 QC0 CLK EN0 DISABLE Pullup CLK EN1 LOGIC Pulldown QC1 DIV SELC POWER-ON RESET Pullup nMR ICS87931BYI REVISION A AUGUST 25, 2010 1 2010 Integrated Device Technology, Inc.ICS87931I LOW SKEW, 1-TO-6, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 1c, 9, 17, 32 ndU.nuse No connect 2VP.ower Analog supply pin DDA Controls the frequency being fed to the output dividers. 3NPtOWER DIpnpu Pullu LVCMOS / LVTTL interface levels. 41CtLK IpnpuP.ullu Clock input. LVCMOS / LVTTL interface levels Active LOW Master reset. When logic LOW, the internal dividers are 5RntM Ipnpu Pullu reset causing the outputs to go low. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 60CtLK IpnpuP.ullu Non-inverting differential clock input Pullup/ 70ntCLK Inpu Inverting differential clock input. V /2 default when left floating. CC Pulldown 8D, 16, 24,25GrNP.owe Power supply ground CLK EN0, Controls the enabling and disabling of the clock outputs. See Table 3B. 10, 11 Ipnput Pullu CLK EN1 LVCMOS / LVTTL interface levels. External feedback. When LOW, selects internal feedback. 1B2 EtXT FIpnpu Pullu When HIGH, selects EXT FB. LVCMOS / LVTTL interface levels. 1V3, 21, 28 P.ower Output supply pins DDO Bank C clock outputs.7 typical output impedance. 114, 15QtC0, QC Outpu LVCMOS / LVTTL interface levels. Selects between the PLL and reference clocks as the input to the 1L8PtLL SEIpnpu Pullu output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVCMOS / LVTTL interface levels. Clock select input. Selects the Phase Detector Reference. 1L9CtLK SEInnpu Pulldow When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 2L0EtXTFB SEInnpuP.ulldow External feedback select. LVCMOS / LVTTL interface levels Bank B clock outputs.7 typical output impedance. 202, 23QtB1, QB Outpu LVCMOS / LVTTL interface levels. Bank A clock outputs.7 typical output impedance. 206, 27QtA1, QA Outpu LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 4A. 2A9DtIV SELInnpu Pulldow LVCMOS / LVTTL interface levels. Determines output divider values for Bank B as described in Table 4A. 3B0DtIV SELInnpu Pulldow LVCMOS / LVTTL interface levels. Determines output divider values for Bank C as described in Table 4A. 3C1DtIV SELInnpu Pulldow LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN R Input Pullup Resistor 5K1 PULLUP R Input Pulldown Resistor 5K1 PULLDOWN Power Dissipation Capacitance C V , V=23.465V 1Fp PD DDA DDO (per output) R Output Impedance 7 OUT ICS87931BYI REVISION A AUGUST 25, 2010 2 2010 Integrated Device Technology, Inc.