LOW SKEW, 1:6 CRYSTAL-TO- ICS83905 LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES Six LVCMOS / LVTTL outputs The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL ICS Fanout Buffer and a member of the HiPerClockS Outputs able to drive 12 series terminated lines HiPerClockS family of High Performance Clock Solutions from IDT. Crystal oscillator interface The low impedance LVCMOS/LVTTL outputs are de- Crystal input frequency range: 10MHz to 40MHz signed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 Output skew: 80ps (maximum) to 12 by utilizing the ability of the outputs to drive two series RMS phase jitter 25MHz, (100Hz - 1MHz): terminated lines. 0.26ps (typical) (V = V = 2.5V) DD DDO The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, Phase noise: mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating Offset Noise Power supply mode. Guaranteed output and part-to-part skew char- 100Hz ............. -129.7 dBc/Hz acteristics along with the 1.8V output capabilities makes the 1kHz ............. -144.4 dBc/Hz ICS83905 ideal for high performance, single ended applica- 10kHz ............. -147.3 dBc/Hz tions that also require a limited output voltage. 100kHz ............. -157.3 dBc/Hz 5V tolerant enable inputs PIN ASSIGNMENTS Synchronous output enables Operating power supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3V core/2.5V output operating supply, mixed 3.3V core/1.8V output operating supply, mixed 2.5V core/1.8V output operating supply 20 19 18 17 16 0C to 70C ambient operating temperature 1 BCLK5 GND 15 ICS83905 Available in both standard (RoHS 5) and lead-free (RoHS 6) GND 2 VDDO 14 20-Lead VFQFN packages 4mm x 4mm x 0.925mm 3 BCLK4 BCLK0 13 body package VDDO 4 GND 12 K Package 5 GND Top View BCLK1 11 6 7 8 9 10 BLOCK DIAGRAM BCLK0 XTAL OUT 1 16 XTAL IN 2 ENABLE 2 15 ENABLE 1 3 GND 14 BCLK5 BCLK1 4 BCLK0 13 VDDO XTAL IN 5 VDDo 12 BCLK4 6 BCLK1 11 GND 7 BCLK2 GND 10 BCLK3 XTAL OUT 8 BCLK2 9 VDD ICS83905 BCLK3 16-Lead SOIC 3.9mm x 9.9mm x 1.38mm body package BCLK4 M Pacakge Top View ENABLE 1 SYNCHRONIZE 16-Lead TSSOP BCLK5 4.4mm x 5.0mm x 0.925mm body package ENABLE 2 SYNCHRONIZE G Pacakge Top View IDT / ICS LVCMOS/LVTTL FANOUT BUFFER 1 ICS83905AM REV. B JANUARY 24, 2008 ENABLE 2 GND XTAL OUT GND XTAL IN BCLK2 ENABLE 1 VDD nc BCLK3ICS83905 LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Neame Tnyp Descriptio XtTAL OUTO.utpu Crystal oscillator interface. XTAL OUT is the output XtTAL INI.npu Crystal oscillator interface. XTAL IN is the input EtNABLE 1, ENABLE 2 Inpu Clock enable. LVCMOS / LVTTL interface levels. See Table 3. BCLK0, BCLK1, BCLK2, O.utput Clock outputs. LVCMOS / LVTTL interface levels BCLK3, BCLK4, BCLK5 Po GrNDP.owe wer supply ground VP.ower Core supply pin DD VP.ower Output supply pin DDO nd/cU.nuse No connect TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN V=93.465V 1Fp DDO Power Dissipation Capacitance C V=82.625V 1Fp PD DDO (per output) V=62V 1Fp DDO V=73.3V 5% DDO R Output Impedance V=72.5V 5% OUT DDO V=01.8V 0.2V 1 DDO TABLE 3. CLOCK ENABLE FUNCTION TABLE Csontrol Inputs Output E2NABLE 1E4NABLEB5CLK0:BCLK BCLK 00 LWOW LO 01 LgOW Togglin 10 TWoggling LO 11Tgoggling Togglin BCLK5 BCLK0:4 ENABLE2 ENABLE1 FIGURE 1. ENABLE TIMING DIAGRAM IDT / ICS LVCMOS/LVTTL FANOUT BUFFER 2 ICS83905AM REV. B JANUARY 24, 2008