OBSOLETE PRODUCT DATASHEET NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc ISL12028, ISL12028A FN8233 Rev 10.00 Real Time Clock/Calendar with I2C Bus and EEPROM August 14, 2015 The ISL12028 device is a low power real time clock with Features clock/calendar, power-fail indicator, clock output and crystal Real Time Clock/Calendar compensation, two periodic or polled alarms (CMOS output), - Tracks time in Hours, Minutes and Seconds intelligent battery backup switching, CPU Supervisor, - Day of the Week, Day, Month and Year integrated 512x8-bit EEPROM configured in 16 bytes per - 3 Selectable Frequency Outputs page. Two Non-Volatile Alarms The oscillator uses an external, low-cost 32.768kHz crystal. - Settable on the Second, Minute, Hour, Day of the Week, The real-time clock tracks time with separate registers for Day, or Month hours, minutes and seconds. The device has calendar - Repeat Mode (Periodic Interrupts) registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year Automatic Backup to Battery or SuperCap correction. - Power Failure Detection - 800nA Battery Supply Current The ISL12028 and ISL12028A Power Control Settings are different. The ISL12028 uses the Legacy Mode Setting, and On-Chip Oscillator Compensation the ISL12028A uses the Standard Mode Setting. - Internal Feedback Resistor and Compensation Applications that have V > V will require only the BAT DD Capacitors ISL12028A. Please refer to Power Control Operation on - 64 Position Digitally Controlled Trim Capacitor 2 page 14 for more details. Also, please refer to I C - 6 Digital Frequency Adjustment Settings to 30ppm Communications During Battery Backup and LVR Operation 512x8 Bits of EEPROM: on page 25 for important details. - 16-Byte Page Write Mode (32 total pages) - 8 Modes of BlockLock Protection Pinout - Single Byte Write Capability ISL12028, ISL12028A (14 LD TSSOP, SOIC) - Data Retention: 50 years TOP VIEW - Endurance: >2,000,000 Cycles Per Byte X1 1 14 V DD CPU Supervisor Functions: X2 2 13 V BAT - Power On Reset, Low Voltage Sense NC 3 12 IRQ/F OUT - Watchdog Timer (0.25s, 0.75s and 1.75s) NC 4 11 NC NC 5 10 NC 2 I C Interface RESET 6 9 SCL - 400kHz Data Transfer Rate GND 7 8 SDA 14 Ld SOIC and 14 Ld TSSOP Packages NC = No internal connection Pb-Free (RoHS Compliant) Applications Utility Meters HVAC Equipment Audio/Video Components Modems Network Routers, Hubs, Switches, Bridges Cellular Infrastructure Equipment Fixed Broadband Wireless Equipment Pagers/PDA POS Equipment Test Meters/Fixtures Office Automation (Copiers, Fax) Home Appliances Computer Products Other Industrial/Medical/Automotive FN8233 Rev 10.00 Page 1 of 29 August 14, 2015ISL12028, ISL12028A Ordering Information V TRIP BSW BIT V BAT RESET PART NUMBER PART POINT DEFAULT VOLTAGE TEMP. RANGE PACKAGE PKG. (Notes 1, 2, 3) MARKING (V) SETTING (V) (C) (Pb-free) DWG. ISL12028IB27Z 12028IB27Z V < V BSW = 1 2.63 -40 to +85 14 Ld SOIC M14.15 DD BAT ISL12028IBZ 12028IBZ V < V BSW = 1 4.38 -40 to +85 14 Ld SOIC M14.15 DD BAT ISL12028IV27Z 12028 IV27Z V < V BSW = 1 2.63 -40 to +85 14 Ld TSSOP M14.173 DD BAT ISL12028IVZ 12028 IVZ V < V BSW = 1 4.38 -40 to +85 14 Ld TSSOP M14.173 DD BAT ISL12028AIB27Z 12028AIB 27Z 2.2 BSW = 0 2.63 -40 to +85 14 Ld SOIC M14.15 (No longer available or supported) ISL12028AIV27Z 2028A IV27Z 2.2 BSW = 0 2.63 -40 to +85 14 Ld TSSOP M14.173 (No longer available or supported) NOTES: 1. Add -T* suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12028, ISL12028A. For more information on MSL please see techbrief TB363 Block Diagram OSC COMPENSATION X1 TIMER BATTERY TIME V FREQUENCY 1Hz DD 32.768kHZ SWITCH CALENDAR KEEPING OSCILLATOR DIVIDER V CIRCUITRY REGISTERS BACK X2 LOGIC (SRAM) IRQ/F SELECT OUT STATUS CONTROL/ SCL CONTROL COMPARE SERIAL REGISTERS REGISTERS ALARM DECODE INTERFACE (EEPROM) LOGIC (SRAM) DECODER ALARM REGS SDA (EEPROM) 8 4k EEPROM WATCHDOG LOW VOLTAGE ARRAY TIMER RESET RESET FN8233 Rev 10.00 Page 2 of 29 August 14, 2015 MASK