ISL23318WFUZ Renesas

DATASHEET ISL23318 FN7887 Rev 0.00 Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP) July 26, 2011 The ISL23318 is a volatile, low voltage, low noise, low power, Features 2 I C Bus, 128 Taps, single digitally controlled potentiometer 128 resistor taps (DCP), which integrates DCP core, wiper switches and control 2 logic on a monolithic CMOS integrated circuit. I C serial interface - No additional level translator for low bus supply The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The - Two address pins allow up to four devices per bus position of the wipers are controlled by the user through the Power supply 2 I C bus interface. The potentiometer has an associated -V = 1.7V to 5.5V analog power supply CC volatile Wiper Register (WR) that can be directly written to and 2 -V = 1.2V to 5.5V I C bus/logic power supply read by the user. The contents of the WR controls the position LOGIC of the wiper. When powered on, the ISL23318s wiper will Wiper resistance: 70 typical V = 3.3V CC always commence at mid-scale (64 tap position). Shutdown Mode - forces the DCP into an end-to-end open The low voltage, low power consumption, and small package circuit and R is shorted to R internally W L of the ISL23318 make it an ideal choice for use in battery Power-on preset to mid-scale (64 tap position) operated equipment. In addition, the ISL23318 has a V LOGIC pin allowing down to 1.2V bus operation, independent from the Shutdown and standby current <2.8A max V value. This allows for low logic levels to be connected CC DCP terminal voltage from 0V to V CC directly to the ISL23318 without passing through a voltage 10k 50kor 100k total resistance level shifter. Extended industrial temperature range: -40C to +125C The DCP can be used as a three-terminal potentiometer or as a 10 Ld MSOP or 10 Ld UTQFN packages two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal Pb-free (RoHS compliant) processing. Applications Gain adjustment in battery powered instruments Trimming sensor circuits Power supply margining RF power amplifier bias compensation 10000 V REF 8000 RH 6000 - VREF M 4000 RW ISL23318 + 2000 ISL28114 RL 0 032 64 96 128 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP FIGURE 2. V ADJUSTMENT REF POSITION, 10k DCP FN7887 Rev 0.00 Page 1 of 19 July 26, 2011 RESISTANCE ()ISL23318 Block Diagram V V LOGIC CC R SCL H POWER-UP SDA INTERFACE, I/O LEVEL CONTROL WR A1 BLOCK SHIFTER AND VOLATILE STATUS A0 REGISTER LOGIC AND WIPER CONTROL CIRCUITRY R L R W GND Pin Configurations Pin Descriptions ISL23318 MSOP UTQFN SYMBOL DESCRIPTION (10 LD MSOP) 2 110 V I C bus /logic supply. Range 1.2V to LOGIC TOP VIEW 5.5V 10 GND V 1 2 1 SCL Logic Pin - Serial bus clock input LOGIC 9 V SCL 2 CC 3 2 SDA Logic Pin - Serial bus data SDA 3 8 RH input/open drain output A0 4 7 RW 4 3 A0 Logic Pin - Hardwire slave address 2 A1 5 6 RL pin for I C serial bus. Range: V or GND LOGIC 5 4 A1 Logic Pin - Hardwire slave address 2 ISL23318 pin for I C serial bus. (10 LD UTQFN) Range: V or GND LOGIC TOP VIEW 6 5 RL DCP low terminal 7 6 RW DCP wiper terminal 8 7 RH DCP high terminal GND SCL 1 9 98 V Analog power supply. CC Range 1.7V to 5.5V SDA V 2 8 CC 10 9 GND Ground pin A0 RH 3 7 A1 RW 4 6 FN7887 Rev 0.00 Page 2 of 19 July 26, 2011 5 10 V RL LOGIC