ISL6269CRZ Renesas

NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc DATASHEET ISL6269 FN9177 Rev 3.00 High-Performance Notebook PWM Controller with Bias Regulator and June 25, 2009 Audio-Frequency Clamp The ISL6269 IC is a Single-Phase Synchronous-Buck PWM Features 3 controller featuring Intersil s Robust Ripple Regulator (R ) 3 High performance R technology technology that delivers truly superior dynamic response to Fast transient response input voltage and output load transients. Integrated MOSFET drivers, 5V LDO and bootstrap diode result in +0.6V Internal Reference fewer components and smaller implementation area. - 0.6% tolerance over the commercial temperature 3 range (0C to +70C) Intersils R technology combines the best features of fixed- - 1.0% tolerance over the industrial temperature range frequency PWM and hysteretic PWM while eliminating many 3 (-40C to +85C) of their shortcomings. R technology employs an innovative Wide input voltage range: +7.0V to +25.0V modulator that synthesizes an AC ripple voltage signal V , R analogous to the output inductor ripple current. The AC signal Output voltage range: +0.6V to +3.3V V enters a window comparator where the lower threshold is R Wide output load range: 0A to 25A the error amplifier output V , and the upper threshold is a COMP Selectable diode emulation mode for increased light load programmable voltage reference V resulting in generation W, efficiency of the PWM signal. The voltage reference V sets the steady W Programmable PWM frequency: 200kHz to 600kHz state PWM frequency. Both edges of the PWM can be Pre-biased output start-up capability modulated in response to input voltage transients and output Internal 5V LDO for self-biasing load transients, much faster than conventional fixed frequency PWM controllers. Unlike a conventional hysteretic converter, Integrated MOSFET drivers and bootstrap diode the ISL6269 has an error amplifier that provides 1% voltage Internal digital soft-start regulation at the FB pin. Power good monitor The ISL6269 has a 1.5ms digital soft-start and can be started PWM minimum frequency above audible spectrum into a pre-biased output voltage. A resistor divider is used to Fault protection program the output voltage setpoint. The ISL6269 can be - Undervoltage protection configured to operate in continuous-conduction-mode (CCM) - Soft crowbar overvoltage protection or diode-emulation-mode (DEM), which improves light-load - Low-side MOSFET r overcurrent protection DS(ON) efficiency. In CCM the controller always operates as a - Over-temperature protection synchronous rectifier however, when DEM is enabled the - Fault identification by PGOOD pull-down resistance low-side MOSFET is permitted to stay off, blocking negative Pb-free (RoHS compliant) current flow into the low-side MOSFET from the output inductor. Applications Pinout PCI express graphical processing unit ISL6269 Auxiliary power rail (16 LD 4x4 QFN) TOP VIEW VRM Network adapter Ordering Information 16 15 14 13 PART TEMP NUMBER PART RANGE PACKAGE PKG. 1 12 PVCC VIN (Note) MARKING (C) (Pb-free) DWG. 2 11 LG VCC ISL6269CRZ* 62 69CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4 GND ISL6269IRZ* 62 69IRZ -40 to +100 16 Ld 4x4 QFN L16.4x4 FCCM 3 10 PGND *Add -T suffix for tape and reel. Please refer to TB347 for details on 4 9 ISEN EN reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ 576 8 special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN9177 Rev 3.00 Page 1 of 14 June 25, 2009 COMP PGOOD FB PHASE FSET UG BOOT VOISL6269 FN9177 Rev 3.00 Page 2 of 14 June 25, 2009 Block Diagram VIN VO GND PACKAGE BOTTOM 5V LDO PWM FREQUENCY FSET CONTROL VCC V REF g V V EN m IN W R PWM Q OVP S V R g V m O V COMP C R UVP BOOT EAEA DRIVER UG FB POR DIGITAL SOFT-START COMP PHASE SHOOT THROUGH ISEN PROTECTION OCP PVCC I OC 30 90 60 DRIVER LG 150OT PGOOD PGND FCCM FIGURE 1. SCHEMATIC BLOCK DIAGRAM PWM CONTROL