DATASHEET TW2964 FN8288 Rev. 3.00 4-CH WD1 (960H)/D1 Compatible Video Decoders and April 11, 2014 Audio Codecs Features Video Decoder Audio Codec WD1 (960H) and D1 compatible video decoding Integrated five audio ADCs processing and one operation and it is programmable each channel audio DAC NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N Provides multi-channel audio mixed analog output combination), PAL (60) support with automatic Support I2S/DSP Master/Slave interface for record format detection output and playback input Software selectable analog inputs allows any of 2 PCM 8/16-bit and u-Law/A-Law 8-bit for audio CVBS per one video ADC word length Built-in analog anti-alias filter Programmable audio sample rate that covers popular frequencies of 8/16/32/44.1/48kHz Four 10-bit ADCs and analog clamping circuit for CVBS input Miscellaneous Fully programmable static gain or automatic gain control for the Y channel Two-wire MPU serial bus interface Programmable white peak control for CVBS Integrated clock PLL for 144/108MHz clock output channel Power save and Power down mode 4-H adaptive comb filter Y/C separation Low power consumption PAL delay line for color phase error correction Single 27MHz crystal for all standards and both Image enhancement with peaking and CTI WD1 and D1 format Digital sub-carrier PLL for accurate color decoding I/O pin compatible with TW2960 (Supply pins are different) Digital Horizontal PLL for synchronization processing and pixel sampling 3.3V tolerant I/O Advanced synchronization processing and sync 1.0V/3.3V power supply detection for handling non-standard and weak 100-pin and 128-pin LQFP packages signal Programmable hue, brightness, saturation, contrast, sharpness Automatic color control and color killer ITU-R 656 like YCbCr (4:2:2) output or time multiplexed output with 36/72/144MHz for WD1 or 27/54/108MHz for D1 format FN8288 Rev. 3.00 Page 1 of 139 April 11, 2014 TW2964 VIN1A VD1 7:0 44HH CCoommbb ADC ADC VViiddeeoo DDeeccooddeerr VD2 7:0 VIN1B VD3 7:0 AIN1 AADDCC DDeecciimmaattiioonn FFiilltteerr VD4 7:0 MPP1 VIN2A MPP2 44HH CCoommbb AADDCC VViiddeeoo DDeeccooddeerr MPP3 VIN2B MPP4 AIN2 ADC ADC DDeecciimmaattiioonn FFiilltteerr CLKPO XTO VIN3A XTI 44HH CCoommbb ADC ADC VViiddeeoo DDeeccooddeerr CLKNO VIN3B SCLK AIN3 AADDCC DDeecciimmaattiioonn FFiilltteerr SDAT IRQ VIN4A 44HH CCoommbb AADDCC ACLKR VViiddeeoo DDeeccooddeerr VIN4B ASYNR ADATR AIN4 ADC Decimation Filter ADC ADATM ACLKP ASYNP AIN5 Decimation Filter ADC ADATP DAC Interpolation Filter AOUT FIGURE 1. TW2964 BLOCK DIAGRAM FN8288 Rev. 3.00 Page 2 of 139 April 11, 2014 MUX MUX MUX MUX Clock PLL Host MPP BT.656 I2S Clock Interface Interface Interface Interface Generator