CM2006-02QR ON Semiconductor

CM2006 Praetorian L-C LCD and Camera EMI Filter Array with ESD Protection Product Description www.onsemi.com The CM2006 connects between the VGA or DVII port connector and the internal analog or digital flat panel controller logic. The CM2006 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with lowcapacitance current steering diodes. QSOP16 All connector interface pins are designed to safely handle the high QR SUFFIX current spikes specified by IEC6100042 Level 4 (8 kV contact CASE 492 discharge). The ESD protection for the DDC, SYNC and VIDEO signal pins is designed to prevent backdrive current when the device MARKING DIAGRAM is powered down while connected to a video source that is powered up. Separate positive supply rails are provided for the VIDEO / SYNC CMDYYWW signals and DDC signals to facilitate interfacing with low voltage CM2006 video controller ICs and microcontrollers to provide design flexibility 02QR in multisupplyvoltage environments. Two Schmitttriggered noninverting buffers redrive and condition the HSYNC and VSYNC signals from the video connector (SYNC1, CM200602QR = Specific Device Code SYNC2). These buffers accept VESA VSIS compliant TTL input YY = Year WW = Work Week signals and convert them to CMOS output levels that swing between ground and V CC. Two Nchannel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a ORDERING INFORMATION lower supply voltage than the monitor. The gate terminals for these Device Package Shipping MOSFETS (V ) should be connected to the supply rail CC DDC (typically 3.3 V, 2.5 V, etc.) that supplies power to the transceivers of CM200602QR QSOP16 2500/Tape & Reel the DDC controller. (PbFree) For information on tape and reel specifications, Features including part orientation and tape sizes, please Includes ESD Protection, LevelShifting, Buffering and Sync refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Impedance Matching VESA VSIS Version 1 Revision 2 Compatible Interface Supports Optional NAVI Signalling Requirements 7 Channels of ESD Protection for all VGA Port Bidirectional Level Shifting NChannel FETs Provided Connector Pins. All Pins Meet IEC6100042 Level 4 for DDC CLK & DDC DATA Channels ESD Requirements (8 kV Contact Discharge) Backdrive Protection on all Lines Very Low Loading Capacitance from ESD Protection Compact 16Lead QSOP Package Diodes on VIDEO Lines (3 pF Maximum) SchmittTriggered Input Buffers for HSYNC and VSYNC Lines These Devices are PbFree and are RoHS Compliant Applications VGA and DVII Ports in: Monitors TVs Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2016 Rev. 4 CM2006/DCM2006 ELECTRICAL SCHEMATIC V V BYP CC CC DDC 8 1 10 DDC OUT1 11 7 DDC OUT2 3 VIDEO 1 4 R R T T VIDEO 2 5 VIDEO 3 6 GND 16 SYNC OUT2 14 GND SYNC OUT1 9 DDC IN1 12 DDC IN2 2 ENABLE 13 SYNC IN1 15 SYNC IN2 PACKAGE / PINOUT DIAGRAM Top View V 1 16 SYNC OUT2 CC ENABLE 2 15 SYNC IN2 VIDEO 1 SYNC OUT1 3 14 VIDEO 2 4 13 SYNC IN1 VIDEO 3 DDC IN2 5 12 GND 6 11 DDC OUT2 V DDC OUT1 7 10 CC DDC BYP DDC IN1 8 9 16 Pin QSOP Table 1. PIN DESCRIPTIONS Lead(s) Name Description 1 V This is a supply input for the SYNC 1 and SYNC 2 level shifters, video protection and the DDC circuits. CC 2 ENABLE Active high enable. Disables the Sync buffer outputs when low. 3 VIDEO 1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the control- ler device and the video connector. 4 VIDEO 2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the control- ler device and the video connector. 5 VIDEO 3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the control- ler device and the video connector. 6 GND Ground reference supply pin. 7 V This is an isolated supply input for the DDC 1 and DDC 2 levelshifting NFET gates. CC DDC 8 BYP An external 0.22 F bypass capacitor is required on this pin. 9 DDC IN1 DDC signal input. Connects to the video connector side of one of the DDC lines.signal output. 10 DDC OUT1 DDC signal output. Connects to the monitor DDC logic. 11 DDC OUT DDC signal output. Connects to the monitor DDC logic. 12 DDC IN2 DDC signal input. Connects to the video connector side of one of the DDC lines 13 SYNC IN1 Sync signal buffer input. Connects to the video connector side of one of the sync lines. 14 SYNC OUT1 Sync signal buffer output. Connects to the monitor SYNC logic. 15 SYNC IN2 Sync signal buffer input. Connects to the video connector side of one of the sync lines. 16 SYNC OUT2 Sync signal buffer output. Connects to the monitor SYNC logic. www.onsemi.com 2