X9221A 64 Taps, 2-Wire Serial Bus Data Sheet August 30, 2006 FN8163.2 DESCRIPTION Dual Digitally Controlled Potentiometer (XDCP) The X9221A integrates two digitally controlled potenti- ometers (XDCP) on a monolithic CMOS integrated FEATURES microcircuit. Two XDCPs in one package The digitally controlled potentiometer is implemented 2-wire serial interface using 63 resistive elements in a series array. Between Register oriented format, 8 registers total each element are tap points connected to the wiper Directly write wiper position terminal through switches. The position of the wiper on Read wiper position the array is controlled by the user through the 2-wire Store as many as four positions per pot bus interface. Each potentiometer has associated with Instruction format it a volatile Wiper Counter Register (WCR) and 2 non- Quick transfer of register contents to resistor volatile Data Registers (DR0:DR1) that can be directly array written to and read by the user. The contents of the Direct write cell WCR controls the position of the wiper on the resistor Endurance100,000 writes per bit per register array through the switches. Power up recalls the con- Resistor array values tents of DR0 to the WCR. 2k, 10k, 50k Resolution: 64 taps each pot The XDCP can be used as a three-terminal potentiom- 20 Ld plastic DIP and 20 Ld SOIC packages eter or as a two-terminal variable resistor in a wide Pb-free plus anneal available (RoHS compliant) variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Pot 0 V CC R0 R1 V /R H0 H0 V SS Wiper Counter Register (WCR) V /R R2 R3 L0 L0 V /R W0 W0 SCL SDA Interface and A0 Control A1 Circuitry 8 A2 A3 Data V /R H1 H1 R0 R1 Wiper Register Counter Array Register Pot 1 (WCR) V /R L1 L1 R2 R3 V /R W1 W1 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.X9221A Ordering Information V LIMITS TEMP PKG. CC PART NUMBER PART MARKING (V) R (k) RANGE (C) PACKAGE DWG. TOTAL X9221AYS X9221AYS 5 10% 2 0 to +70 20 Ld SOIC (300MIL) MDP0027 X9221AYSZ (Note) X9221AYS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AYSI* X9221AYSI -40 to +85 20 Ld SOIC (300MIL) MDP0027 X9221AYSIZ* (Note) X9221AYSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AWS* X9221AWS 10 0 to +70 20 Ld SOIC (300MIL) MDP0027 X9221AWSZ* (Note) X9221AWS Z 0 to +70 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AWSI* X9221AWSI -40 to +85 20 Ld SOIC (300MIL) MDP0027 X9221AWSIZ* (Note) X9221AWSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 X9221AUP X9221AUP 50 0 to +70 20 Ld PDIP MDP0031 X9221AUPZ (Note) X9221AUPZ 0 to +70 20 Ld PDIP (Pb-Free) MDP0031 X9221AUPI X9221AUPI -40 to +85 20 Ld PDIP MDP0031 X9221AUPIZ (Note) X9221AUPIZ -40 to +85 20 Ld PDIP (Pb-Free) MDP0031 X9221AUSI* X9221AUSI -40 to +85 20 Ld SOIC (300MIL) MDP0027 X9221AUSIZ* (Note) X9221AUSI Z -40 to +85 20 Ld SOIC (300MIL) (Pb-Free) MDP0027 *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PIN DESCRIPTIONS Potentiometer Pins Host Interface Pins V /R (V /R -V /R ), V /R (V /R -V /R ) H H H0 H0 H1 H1 L L L0 L0 L1 L1 The V /R and V /R inputs are equivalent to the ter- H H L L Serial Clock (SCL) minal connections on either end of a mechanical The SCL input is used to clock data into and out of the potentiometer. X9221A. V /R (V /R -V /R ) W W W0 W0 W1 W1 Serial Data (SDA) The wiper outputs are equivalent to the wiper output of SDA is a bidirectional pin used to transfer data into a mechanical potentiometer. and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or PIN CONFIGURATION open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical val- DIP/SOIC ues, refer to the guidelines for calculating typical val- ues on the bus pull-up resistors graph. V /R 1 20 V W0 W0 CC V /R 2 19 RES L0 L0 Address V /R 3 18 RES H0 L0 The Address inputs are used to set the least signifi- A0 4 17 RES cant 4 bits of the 8-bit slave address. A match in the A2 5 16 A1 slave address serial data stream must be made with X9221A V /R 6 15 A3 W1 W1 the Address input in order to initiate communication V /R 7 14 SCL with the X9221A L1 L1 V /R 8 13 RES H1 H1 SDA 9 12 RES V SS 10 11 RES FN8163.2 2 August 30, 2006