X9260 Dual Supply/Low Power/256-Tap/SPI bus Data Sheet August 29, 2006 FN8170.3 DESCRIPTION Dual Digitally-Controlled (XDCP) Potentiometers The X9260 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS FEATURES integrated circuit. DualTwo Separate Potentiometers The digitally controlled potentiometer is implemented 256 Resistor Taps/pot0.4% Resolution using 255 resistive elements in a series array. SPI Serial Interface for Write, Read, and Transfer Between each element are tap points connected to the Operations of the Potentiometer wiper terminal through switches. The position of the Wiper Resistance, 100 typical V+ = 5V, wiper on the array is controlled by the user through the V- = -5V SPI bus interface. Each potentiometer has associated 4 Nonvolatile Data Registers for Each with it a volatile Wiper Counter Register (WCR) and a Potentiometer four nononvolatile Data Registers that can be directly Nonvolatile Storage of Multiple Wiper Positions written to and read by the user. The contents of the Power-on Recall. Loads Saved Wiper Position on WCR controls the position of the wiper on the resistor Power-up. array though the switches. Power-up recalls the Standby Current <5A Max contents of the default Data Register (DR0) to the V : 2.7V to 5.5V Operation CC WCR. 50k , 100k Versions of End to End Resistance 100 yr. Data Retention The XDCP can be used as a three-terminal Endurance: 100,000 Data Changes per Bit per potentiometer or as a two terminal variable resistor in Register a wide variety of applications including control, 24 Ld SOIC parameter adjustments, and signal processing. Low Power CMOS Power Supply V = 2.7V to 5.5V CC V+ = 2.7V to 5.5V V- = -2.7V to -5.5V Pb-Free Plus Anneal Available (RoHS Compliant) FUNCTIONAL DIAGRAM V V R R + CC H0 H1 Write Read Address Transfer Power-on Recall Data Inc/Dec Status Bus SPI Wiper Counter Bus Interface Registers (WCR) Interface and Control Data Registers (DR0-DR3) Control V V- R R R R SS W0 L0 W1 L1 50k or 100k versions CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT ISL22424X9260 Ordering Information POTENTIOMETER PART ORGANIZATION TEMPERATURE PART NUMBER MARKING V LIMITS (V) (k ) RANGE (C) PACKAGE PKG. DWG. CC X9260TS24I X9260TS I 5 10% 100 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9260TS24IZ (Note) X9260TS ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9260US24 X9260US 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9260US24Z (Note) X9260US Z 0 to +70 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9260TS24I-2.7 X9260TS G 2.7 to 5.5 100 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9260TS24IZ-2.7 (Note) X9260TS ZG -40 to +85 24 Ld SOIC (300 mil) M24.3 (Pb-free) X9260US24-2.7 X9260US F 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9260US24Z-2.7 (Note) X9260US ZF 0 to +70 24 Ld SOIC (300 mil) M24.3 (Pb-free) *AddT1 suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. DETAILED FUNCTIONAL DIAGRAM R R R H0 L0 W0 V CC V + Power-on Recall Pot 0 R R 0 1 HOLD Wiper Counter CS Register SCK INTERFACE (WCR) R R 2 3 SO AND CONTROL SI CIRCUITRY A0 50K and 100K A1 256-taps 8 Power-on Recall Data WP R R 0 1 Wiper Resistor Counter Array Register Pot 1 (WCR) R R 2 3 V R R R SS L1 H1 W1 V- FN8170.3 2 August 29, 2006