NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ZL6100 DATASHEET FN76850 ZL2006 Rev. 1.00 December 15, 2010 Adaptive Digital DC-DC Controller with Drivers and Current Sharing Description Features Power Conversion The ZL2006 is a digital DC-DC controller with Efficient synchronous buck controller integrated MOSFET drivers. Current sharing allows Adaptive light load efficiency optimization multiple devices to be connected in parallel to source 3 V to 14 V input range loads with very high current demands. Adaptive 0.54 V to 5.5 V output range (with margin) performance optimization algorithms improve power 1% output voltage accuracy conversion efficiency across the entire load range. Internal 3 A MOSFET drivers Zilker Labs Digital-DC technology enables a blend Fast load transient response of power conversion performance and power Current sharing and phase interleaving management features. Sn ap shot parameter capture RoHS compliant (6 x 6 mm) QFN package The ZL2006 is designed to be a flexible building block for DC power and can be easily adapted to designs Power Management ranging from a single-phase power supply operating Digital soft start / stop from a 3.3 V input to a multi-phase supply operating Precision delay and ramp-up Power good / enable from a 12 V input. The ZL2006 eliminates the need for Voltage tracking, sequencing, and margining complicated power supply managers as well as Voltage / current / temperature monitoring numerous external discrete components. 2 I C/SMBus interface, PMBus compatible All operating features can be configured by simple pin- Output voltage and current protection strap/resistor selection or through the SMBus serial Internal non-volatile memory (NVM) interface. The ZL2006 uses the PMBus protocol for communication with a host controller and the Digital- Applications DC bus for communication between other Zilker Labs Servers / storage equipment devices. Telecom / datacom equipment Power supplies (memory, DSP, ASIC, FPGA) FN6850 Rev. 1.00 Page 1 of 45 December 15, 2010 ZL2006 EN PG CFG UVLO V25 VR VDD DLY FC ILIM 100 V = 3.3V OUT 95 V = 1.5V OUT V 90 LDO SS VTRK POWER 85 MANAGEMENT MGN BST SYNC 80 GH DDC DRIVER SW 75 GL NON- 70 VSEN+ PWM VOLATILE VSEN- CONTROLLER MEMORY 65 CURRENT ISENA SENSE ISENB 60 SCL MONITOR TEMP V = 12V 2 IN I C SDA SENSOR 55 ADC f = 400kHz SW SALRT Circuit of Figure 4 50 0 2 4 6 8 10 12 14 16 18 20 SA XTEMP PGND SGND DGND Load Current (A) Figure 1. Block Diagram Figure 2. Efficiency vs. Load Current FN6850 Rev. 1.00 Page 2 of 45 December 15, 2010 Efficiency (%)