6A Digital Synchronous Step-Down DC/DC Converter with Auto Compensation ZL2101 Features The ZL2101 is a 6A digital converter with auto compensation and Integrated MOSFET Switches integrated power management that combines an integrated 6A Continuous Output Current synchronous step-down DC/DC converter with key power 1% Output Voltage Accuracy management functions in a small package, resulting in a flexible and integrated solution. Auto Compensation Snapshot Parametric Capture The ZL2101 can provide an output voltage from 0.54V to 5.5V (with margin) from an input voltage between 4.5V and 14V. 2 I C/SMBus Interface, PMBus Compatible Internal low r synchronous power MOSFETs enable the DS(ON) Internal Non-Volatile Memory (NVM) ZL2101 to deliver continuous loads up to 6A with high efficiency. An internal Schottky bootstrap diode reduces discrete Applications component count. The ZL2101 also supports phase spreading to reduce system input capacitance. Telecom, Networking, Storage equipment Test and Measurement Equipment Power management features such as digital soft-start delay and ramp, sequencing, tracking, and margining can be configured by Industrial Control Equipment simple pin-strapping or through an on-chip serial port. The 5V and 12V Distributed Power Systems ZL2101 uses the PMBus protocol for communication with a host controller and the Digital-DC bus for interoperability Related Literature between other Zilker Labs devices. AN2010 Thermal and Layout Guidelines for Digital-DC Products AN2033 Zilker Labs PMBus Command Set - DDC Products AN2035 Compensation Using CompZL 100 V = 3.3V OUT 90 80 70 60 V = 12V IN f = 200kHz SW 50 L = 6H 40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 I (A) OUT FIGURE 1. ZL2101 EFFICIENCY January 23, 2012 CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved FN7730.0 Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ZL2102 EFFICIENCY (%)ZL2101 Typical Application Circuit The following application circuit represents a typical implementation of the ZL2101. For PMBus operation, it is recommended to tie the enable pin (EN) to SGND. C RA F.B. 4.7F V IN 12V C C C DD 25 R 2.2F 10F 4.7F DDC Bus C IN ENABLE 100F C B 1 PG VDDP 27 PGOOD 47nF 2 DGND BST 26 3 SYNC SW 25 4 VSET SW 24 LOUT 5 SA ZL2106 SW 23 2.2H ZL2101 V OUT 6 SCL SW 22 2 I C/ 3.3V 7 SDA SW 21 SMBus 8 SALRT SW 20 COUT 150F 9 FC PGND 19 Notes: Ferrite bead is optional for input noise suppression. The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices connected. The 10 k default value, assuming a maximum of 100 pF per device, provides the necessary 1 s pull-up rise time. Please refer to the Digital-DC Bus section for more details. 2 The I C/SMBus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices 2 connected. Please refer to the I C/SMBus specifications for more details. FIGURE 2. 12V TO 3.3V/6A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP) Block Diagram V IN 2.5V 5V 7V BST LDO LDO LDO EN PG MGN PWM VSET Power Control CFG Mgmt & SS V OUT SW Drivers VTRK DDC DDC Bus VSEN NVM SA SMBus FIGURE 3. BLOCK DIAGRAM FN7730.0 2 January 23, 2012 ePAD (SGND) SDA 36 10 CFG EN V2P5 SCL 35 11 SS MGN SALRT 12 VTRK DDC 34 VRA V2P5 13 VSEN 33 VRA 32 14 SGND VR 31 15 PGND SYNC VR 16 PGND VDDS 30 VDDS 29 17 PGND VDDP 28 18 PGND VDDP VDDP PGND