NOT RECOMMENDED FOR NEW DESIGNS DATASHEET RECOMMENDED REPLACEMENT PART ZL6105 ZL2008 FN6859 Rev 4.00 Digital DC/DC Controller with Drivers and Pin-Strap Current Sharing April 29, 2011 The ZL2008 is a digital power controller with integrated Features MOSFET drivers. Current sharing allows multiple devices to be connected in parallel to source loads with very high current Power Conversion demands. Adaptive performance optimization algorithms Efficient synchronous buck controller improve power conversion efficiency. Zilker Labs Digital-DC Adaptive light load efficiency optimization technology enables a blend of power conversion performance and power management features. 3V to 14V input range 0.54V to 5.5V output range (with margin) The ZL2008 is designed to be a flexible building block for DC power and can be easily adapted to designs ranging from a POLA and DOSA voltage trim modes single-phase power supply operating from a 3.3V input to a 1% output voltage accuracy multi-phase supply operating from a 12V input. The ZL2008 eliminates the need for complicated power supply managers Internal 3A MOSFET drivers as well as numerous external discrete components. Fast load transient response Key operating features can be configured by pin-straps, Current sharing and phase interleaving including compensation, current sharing and output voltage. Snapshot parameter capture 2 The ZL2008 uses the I C/SMBus with PMBus protocol for RoHS compliant (6mmx6mm) QFN package communication with a host controller and the Digital-DC bus for communication between Zilker Labs devices. Power Management Digital soft-start/stop Applications Precision delay and ramp-up Servers/storage equipment Power good/enable Telecom/datacom equipment Voltage tracking, sequencing and margining Power supply modules Voltage, current and temperature monitoring 2 I C/SMBus interface, PMBus compatible Output voltage and current protection Internal non-volatile memory (NVM) Block Diagram Efficiency vs Load Current 100 EN PG CFG UVLO V25 VR VDD DLY FC ILIM V = 3.3V OUT V = 1.5V 95 OUT 90 V LDO SS 85 VTRK POWER MANAGEMENT MGN 80 BST SYNC GH DDC DRIVER 75 SW GL 70 NON- VSEN+ PWM VOLATILE VSEN- CONTROLLER 65 MEMORY CURRENT ISENA SENSE 60 ISENB V = 12V IN SCL MONITOR TEMP 2 55 I C f = 400kHz SW SDA SENSOR ADC Circuit of Figure 4 SALRT 50 0 4 10 14 16 18 20 2 6812 Load Current (A) SA XTEMP PGND SGND DGND FIGURE 1. BLOCK DIAGRAM FIGURE 2. EFFICIENCY vs LOAD CURRENT FN6859 Rev 4.00 Page 1 of 43 April 29, 2011 Efficiency (%)ZL2008 Table of Contents Absolute Maximum Ratings . 4 Thermal Information . 4 Recommended Operating Conditions . 4 Electrical Specifications 4 Pin Configuration .7 Pin Descriptions . 7 Typical Application Circuit . 9 ZL2008 Overview . 10 Digital-DC Architecture . 10 Power Conversion Overview . 11 Power Management Overview . 11 Multi-mode Pins . 12 Power Conversion Functional Description 12 Internal Bias Regulators and Input Supply Connections . 12 High-side Driver Boost Circuit 12 Output Voltage Selection . 13 Start-up Procedure . 15 Soft-start Delay and Ramp Times 15 Power Good 16 Switching Frequency and PLL . 17 Power Train Component Selection . 18 Current Limit Threshold Selection 21 Loop Compensation . 22 Non-linear Response (NLR) Settings 24 Efficiency Optimized Driver Dead-time Control . 24 Adaptive Diode Emulation 24 Adaptive Frequency Control . 24 Power Management Functional Description 25 Input Undervoltage Lockout . 25 Output Overvoltage Protection . 26 Output Pre-Bias Protection 26 Output Overcurrent Protection . 26 Thermal Overload Protection 27 Voltage Tracking 27 Voltage Margining . 28 I2C/SMBus Communications 28 I2C/SMBus Device Address Selection . 29 Digital-DC Bus 30 Phase Spreading 30 Output Sequencing 31 Fault Spreading . 31 Temperature Monitoring Using the XTEMP Pin .31 Active Current Sharing . 31 Phase Adding/Dropping 34 Monitoring via I2C/SMBus 35 Snapshot Parameter Capture . 35 Non-Volatile Memory and Device Security Features . 35 Pin-strap Current Sharing Configuration 35 SMBus Address (SA0, SA1 Pins) . 36 Current Share Pin-Straps (CFG0, CFG2 Pins) . 36 SYNC Clock (CFG1 Pin) . 36 FN6859 Rev 4.00 Page 2 of 43 April 29, 2011