CY28411 CY28411 Clock Generator for Intel Alviso Chipset 33 MHz PCI clock Features Low-voltage frequency select input Compliant to Intel CK410M 2 I C support with readback capabilities Supports Intel Pentium-M CPU Ideal Lexmark Spread Spectrum profile for maximum Selectable CPU frequencies electromagnetic interference (EMI) reduction Differential CPU clock pairs 3.3V power supply 100 MHz differential SRC clocks 56-pin SSOP and TSSOP packages 96 MHz differential dot clock CPU SRC PCI REF DOT96 USB 48 48 MHz USB clocks x2 / x3 x7 / x8 x 6 x 1 x 1 x 1 Block Diagram Pin Configuration VDD REF VDD PCI 1 56 PCI2 XIN XTAL REF VSS PCI 2 55 PCI STP XOUT OSC PLL Ref Freq PCI3 3 54 CPU STP VDD CPU PCI4 4 53 FS C/TEST SEL CPUT 0:1 , CPUC 0:1 , CPU STP Divider PLL1 CPU(T/C)2 ITP PCI5 5 52 REF Network PCI STP VDD SRC VSS PCI 6 51 VSS REF SRCT 0:6 , SRCC 0:6 VDD PCI 7 50 XIN FS C:A VTT PWRGD PCIF0/ITP EN 8 49 XOUT PCIF1 9 48 VDD REF IREF VTT PWRGD /PD 10 47 SDATA VDD PCI VDD 48 11 46 SCLK PCI 2:5 USB 48/FS A 12 45 VSS CPU VDD PCIF VSS 48 13 44 CPUT0 PCIF 0:1 DOT96T 14 43 CPUC0 DOT96C 15 42 VDD CPU PD VDD 48 MHz FS B/TEST MODE 16 41 CPUT1 DOT96T SRCT0 17 40 CPUC1 PLL2 DOT96C SRCC0 18 39 IREF USB 48 SRCT1 19 38 VSSA SRCC1 20 37 VDDA VDD SRC 21 36 CPUT2 ITP/SRCT7 SRCT2 22 35 CPUC2 ITP/SRCC7 SRCC2 23 34 VDD SRC SRCT3 24 33 SRCT6 SRCC3 25 32 SRCC6 SRC4 SATAT 26 31 SRCT5 2 SDATA I C SRC4 SATAC 27 30 SRCC5 SCLK Logic VDD SRC 28 29 VSS SRC 56 SSOP/TSSOP ........................ Document : 38-07594 Rev. *B Page 1 of 18 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY28411 Pin Definitions Pin No. Name Type Description 54 CPU STP I, PU 3.3V LVTTL input for CPU STP active low. 44,43,41,40 CPUT/C O, DIF Differential CPU clock outputs. 36,35 CPUT2 ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output. CPUC2 ITP/SRCC7 ITP EN = 0 VTT PWRGD assertion = SRC7 ITP EN = 1 VTT PWRGD assertion = CPU2 14,15 DOT96T, DOT96C O, DIF Fixed 96 MHz clock output. 12 FS A/USB 48 I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48 MHz clock output. Refer to DC Electrical Specifications table for Vil FS and Vih FS specifications. 16 FS B/TEST MODE I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z, 1 = Ref/N Refer to DC Electrical Specifications table for Vil FS and Vih FS specifications. 53 FS C/TEST SEL I 3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled to V when VTT PWRGD is asserted low. IMFS C Refer to DC Electrical Specifications table for V ,V ,V specifi- ILFS C IMFS C IHFS C cations. 39 IREF I A precision resistor is attached to this pin, which is connected to the internal current reference. 56,3,4,5 PCI O, SE 33 MHz clocks. 55 PCI STP I, PU 3.3V LVTTL input for PCI STP active low. 8 PCIF0/ITP EN I/O, SE 33 MHz clock/CPU2 select (sampled on the VTT PWRGD assertion). 1 = CPU2 ITP, 0 = SRC7 9 PCIF1 O, SE 33 MHz clocks. 52 REF O, SE Reference clock. 3.3V 14.318-MHz clock output. 46 SCLK I SMBus-compatible SCLOCK. 47 SDATA I/O SMBus-compatible SDATA. 26,27 SRC4 SATAT, O, DIF Differential serial reference clock. Recommended output for SATA. SRC4 SATAC 24,25,22,23, SRCT/C O, DIF Differential serial reference clocks. 19,20,17,18, 33,32,31,30 11 VDD 48 PWR 3.3V power supply for outputs. 42 VDD CPU PWR 3.3V power supply for outputs. 1,7 VDD PCI PWR 3.3V power supply for outputs. 48 VDD REF PWR 3.3V power supply for outputs. 21,28,34 VDD SRC PWR 3.3V power supply for outputs. 37 VDDA PWR 3.3V power supply for PLL. 13 VSS 48 GND Ground for outputs. 45 VSS CPU GND Ground for outputs. 2,6 VSS PCI GND Ground for outputs. 51 VSS REF GND Ground for outputs. 29 VSS SRC GND Ground for outputs. 38 VSSA GND Ground for PLL. 10 VTT PWRGD /PD I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB 48/FS A, FS B, FS C/TEST SEL and PCIF0/ITP EN inputs. After VTT PWRGD (active low) assertion, this pin becomes a real-time input for asserting power down (active high). 50 XIN I 14.318 MHz crystal input. 49 XOUT O, SE 14.318 MHz crystal output.......................Document : 38-07594 Rev. *B Page 2 of 18