Si5020 SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC Features Complete high-speed, low-power, CDR solution includes the following: Supports OC-48/12/3, STM-16/4/1, Exceeds all SONET/SDH jitter Gigabit Ethernet, and 2.7 Gbps FEC specifications Low Power270 mW (TYP OC-48) Jitter generation 2.9 mUI (Typ) Small footprint: 4 x 4 mm rms DSPLL eliminates external loop Device powerdown Ordering Information: filter components Loss-of-lock indicator See page 18. 3.3 V tolerant control inputs Single 2.5 V Supply Applications Pin Assignments SONET/SDH/ATM routers SONET/SDH test equipment Si5020 Add/drop multiplexers Optical transceiver modules Digital cross connects SONET/SDH regenerators Gigabit Ethernet interfaces Board level serial links 20 19 18 17 16 Description REXT 1 15 PWRDN VDD 2 14 The Si5020 is a fully-integrated low-power clock and data recovery (CDR) VDD GND GND 3 13 DOUT+ IC designed for high-speed serial communication systems. It extracts timing Pad Connection REFCLK+ 4 12 DOUT information and data from a serial input at OC-48/12/3, STM-16/4/1, or REFCLK 5 11 VDD Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error 6 7 8 9 10 correction (FEC). DSPLL technology eliminates sensitive noise entry points, making the PLL less susceptible to board-level interaction and helping to Top View ensure optimal jitter performance. The Si5020 represents a new standard in low jitter, low power, and small size for high-speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (40 to 85 C). Functional Block Diagram LOL TM DSPLL DI N + DOUT + BUF Phase-Locked BUF Retimer DI N 2 2 DOUT Loop PWRDN/CAL CLKOUT + Bias BUF 2 2 2 CLKOUT REXT RATESEL1-0 RE F CLK I N + RE F CLK I N Rev. 1.6 2/15 Copyright 2015 by Silicon Laboratories Si5020 Not Recommended for New Designs LOL RATESEL1 VDD RATESEL0 GND GND DIN+ CLKOUT+ DIN CLKOUTSi5020 2 Rev. 1.6 Not Recommended for New Designs