SI5310-C-GM Silicon Labs

Si5310 PRECISION CLOCK MULTIPLIER/REGENERATOR IC Features Complete precision clock multiplier and clock regenerator device: Performs clock multiplication to one Regenerates a clean, jitter- of two frequency ranges: attenuated version of input clock 150167 MHz or 600668 MHz DSPLL technology provides Jitter generation as low as superior jitter performance 0.5 ps for 622 MHz output rms Small footprint: 4 x 4 mm Accepts input clock from Low power: 310 mW typical 9.4668 MHz Ordering Information: ROHS-compliant Pb-free packaging option available See page 21. Applications SONET/SDH systems Optical transceiver modules Pin Assignments Terabit routers Gigabit Ethernet systems Si5310 Digital cross connects Fibre channel Description The Si5310 is a fully integrated low-power clock multiplier and clock 20 19 18 17 16 regenerator IC. The clock multiplier generates an output clock that is an REXT 1 15 PWRDN integer multiple of the input clock. The clock regenerator operates VDD 2 14 VDD simultaneously, creating a clean version of the input clock by using the GND GND 3 13 CLKOUT+ clock synthesis phase-locked loop (PLL) to remove unwanted jitter and Pad REFCLK+ 4 12 CLKOUT square up the input clocks rising and falling edges. The Si5310 uses REFCLK 5 11 VDD Silicon Laboratories patented DSPLL architecture to achieve superior 6 7 8 9 10 jitter performance while eliminating the analog loop filter found in traditional PLL designs with a digital signal-processing algorithm. The Si5310 represents a new standard in low jitter, small size, low power, and ease-of-use for clock devices. It operates from a single 2.5 V supply over the industrial temperature range (40 to 85 C). Functional Block Diagram 2 CLKOUT+ Regeneration BUF CLKOUT Calibration PWRDN/CAL DSPLL 2 CLKIN+ Phase-Locked 2 MULTOUT+ BUF BUF CLKIN MULTOUT Loop LOL Bias Gen 2 REXT REFCLK+ MULTSEL REFCLK Rev. 1.4 2/15 Copyright 2015 by Silicon Laboratories Si5310 LOL NC VDD MULTSEL GND GND CLKIN+ MULTOUT+ CLKIN MULTOUTSi5310 2 Rev. 1.4