SI5317B-C-GMR Silicon Labs

Si5317 PIN-CONTROLLED 1711 MHZ JITTER CLEANING CLOCK Features Provides jitter attenuation for any clock Selectable output clock signal frequency format: LVPECL, LVDS, CML or CMOS One clock input / two clock outputs Single supply: 1.8, 2.5, or 3.3 V Input/output frequency range: 1711 MHz Loss of lock and loss of signal alarms Ultra low jitter: 300 fs (12 kHz20 MHz) typical VCO freeze during LOS/LOL Simple pin control interface On-chip voltage regulator with high PSRR Selectable loop bandwidth for jitter attenuation: 60 Hz8.4 kHz Small size: 6 x 6 mm, 36-QFN Meets OC-192 GR-253-CORE jitter Wide temperature range: 40 to specifications +85 C Ordering Information: Applications See page 40. Data converter clocking Switches and routers Wireless infrastructure Medical instrumentation Networking, SONET/SDH Test and measurement Pin Assignments Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 711 MHz and generates two low jitter clock outputs at the same frequency. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317 is based on Silicon Laboratories 3rd-generation DSPLL technology, which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user selectable, providing jitter performance optimization at the application level. Functional Block Diagram Rev. 1.1 4/11 Copyright 2011 by Silicon Laboratories Si5317Si5317 2 Rev. 1.1