Product Information

Si5317C-C-GM

Si5317C-C-GM electronic component of Silicon Labs

Datasheet
Standard Clock Oscillators Pin-Program. Jitter Cleaning Clock

Manufacturer: Silicon Labs
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 18.2505 ea
Line Total: USD 18.25

3857 - Global Stock
Ships to you between
Thu. 23 May to Mon. 27 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
3857 - WHS 1


Ships to you between Thu. 23 May to Mon. 27 May

MOQ : 1
Multiples : 1

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Si5317C-C-GM
Silicon Labs

1 : USD 18.8025
10 : USD 17.434
25 : USD 16.3415
50 : USD 15.5135
100 : USD 14.904
250 : USD 14.8005

     
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Si5317 PIN-CONTROLLED 1711 MHZ JITTER CLEANING CLOCK Features Provides jitter attenuation for any clock Selectable output clock signal frequency format: LVPECL, LVDS, CML or CMOS One clock input / two clock outputs Single supply: 1.8, 2.5, or 3.3 V Input/output frequency range: 1711 MHz Loss of lock and loss of signal alarms Ultra low jitter: 300 fs (12 kHz20 MHz) typical VCO freeze during LOS/LOL Simple pin control interface On-chip voltage regulator with high PSRR Selectable loop bandwidth for jitter attenuation: 60 Hz8.4 kHz Small size: 6 x 6 mm, 36-QFN Meets OC-192 GR-253-CORE jitter Wide temperature range: 40 to specifications +85 C Ordering Information: Applications See page 40. Data converter clocking Switches and routers Wireless infrastructure Medical instrumentation Networking, SONET/SDH Test and measurement Pin Assignments Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications 36 35 34 33 32 31 30 29 28 that require jitter attenuation without clock multiplication. The Si5317 accepts a RST 1 27 FRQSEL3 single clock input ranging from 1 to 711 MHz and generates two low jitter clock FRQTBL 2 26 FRQSEL2 outputs at the same frequency. The clock frequency range and loop bandwidth are 3 25 FRQSEL1 LOS selectable from a simple look-up table. The Si5317 is based on Skyworks NC 4 24 FRQSEL0 GND Solutions 3rd-generation DSPLL technology, which provides jitter attenuation on VDD 5 23 BWSEL1 Pad any frequency in a highly integrated PLL solution that eliminates the need for XA 6 22 BWSEL0 external VCXO and loop filter components. The DSPLL loop bandwidth is user XB 7 21 NC GND 8 20 INC selectable, providing jitter performance optimization at the application level. NC 9 19 DEC 10 11 12 13 14 15 16 17 18 Functional Block Diagram XTAL/Clock Clock Out1 Clock In DSPLL Signal Format 1:0 Clock Out2 Status/Control High VDD (1.8, 2.5, 3.3 V) PSRR GND Regulator Frequency Table Loss of Lock Frequency Select 3:0 Loss of Signal Bandwidth Select 1:0 XTAL/Clock Rate 1:0 Phase Skew INC/DEC Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 21, 2021 VDD NC RATE0 CKOUT2+ NC CKOUT2- NC SFOUT0 DBL2 BY VDD RATE1 GND CKIN+ SFOUT1 CKIN CKOUT1 LOL CKOUT1+Si5317 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 21, 2021

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