Si5328 ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER Features Fully-compliant with ITU-T Dual clock outputs with G.8262, EEC options 1 and 2. selectable signal format (LVPECL, LVDS, CML, CMOS) Generates any frequency from 8kHz to 808MHz. LOL, LOS, FOS alarm outputs 2 Ultra-low jitter clock outputs with I C or SPI programmable jitter generation as low as 0.3 ps On-chip voltage regulator for rms (12 kHz20 MHz) 2.5 10% or 3.3 V 10% Integrated loop filter with operation Ordering Information: selectable loop bandwidth Small size: 6 x 6 mm 36-lead See page 63. (0.1 Hz 1 to 10 Hz) QFN Dual clock inputs with manual or Pb-free, ROHS compliant automatically controlled hitless Pin Assignments switching Applications G.8262 Synchronous Ethernet, Carrier Ethernet switches, 36 35 34 33 32 31 30 29 28 EEC options 1 and 2 routers RST 1 27 SDI NC 2 26 A2 SS GbE/10GbE/100GbE INT C1B 3 25 A1 Synchronous Ethernet C2B 4 24 A0 GND VDD 5 23 SDA SDO Pad XA 6 22 SCL Description XB 7 21 CS CA GND 8 20 NC NC 9 19 NC The Si5328 is a jitter-attenuating precision clock multiplier for 10 11 12 13 14 15 16 17 18 Synchronous Ethernet applications requiring sub 1 ps jitter performance and ultra-low loop bandwidth. When combined with a low-wander, low- jitter reference oscillator, the Si5328 meets all of the wander, MTIE, TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328 accepts two input clocks ranging from 8 kHz to 710 MHz and generates two output clocks ranging from 8 kHz to 808 MHz. The two outputs are divided down separately from a common source. The Si5328 can also use the TCXO as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range. The Si5328 input clock 2 frequency and clock multiplication ratio are programmable through an I C or SPI interface. The Si5328 is based on Skyworks Solutions third-generation DSPLL technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for providing clock multiplication and jitter attenuation in high-performance, Synchronous Ethernet timing applications. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 27, 2021 VDD CMODE RATE0 CKOUT2+ CKIN2+ CKOUT2 CKIN2 NC NC VDD RATE1 GND CKIN1+ NC CKIN1 CKOUT1 LOL CKOUT1+Si5328 Functional Block Diagram TCXO or Refclock Hitless Switching CKIN1 N31 Mux N1 LS CKOUT1 CKIN2 N32 DSPLL N1 HS N2 LS CKOUT2 Refclock N2 Loss of Signal/ VDD (2.5 or 3.3 V) Frequency Offset Signal Detect Control GND Loss of Lock 2 Clock Select I C/SPI Port Device Interrupt Rate Select 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice August 27, 2021