34 35 36 37 38 39 40 41 42 43 44 Si53313 DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/ LEVEL TRANSLATOR (<1.25 GHZ) Features 2 independent banks of 5x Output clock division: /1, /2, /4 (dc to differential outputs 725 MHz for /2 and /4) Ultra-low additive jitter: 45 fs rms Independent V and V : DD DDO Wide frequency range: 1.8/2.5/3.3 V dc to 1.25 GHz Excellent power supply noise Any-format input with pin selectable rejection (PSRR) output formats: LVPECL, Low Power Small size: 44-QFN (7 mm x 7 mm) LVPECL, LVDS, CML, HCSL, RoHS compliant, Pb-free LVCMOS Industrial temperature range: Asynchronous output enable 40 to +85 C Low output-output skew: <70 ps Ordering Information: See page 27. Applications High-speed clock distribution Storage Ethernet switch/router Telecom Pin Assignments Optical Transport Network (OTN) Industrial SONET/SDH Servers Si53313 PCI Express Gen 1/2/3 Backplane clock distribution Description DIVA 1 33 DIVB 2 32 SFOUTA 1 The Si53313 is an ultra low jitter dual 1:5 differential buffer with pin-selectable SFOUTB 1 3 31 SFOUTA 0 SFOUTB 0 output clock signal format and divider selection. The Si53313 utilizes Skyworks Q2 4 30 Q7 5 29 Q2 Q7 Solutions advanced CMOS technology to fanout clocks from dc to 1.25 GHz with GND 6 28 NC GND PAD guaranteed low additive jitter, low skew, and low propagation delay variability. The 7 27 Q1 Q8 8 26 Q1 Q8 Si53313 features minimal cross-talk and provides superior supply noise rejection, 9 25 Q9 Q0 simplifying low jitter clock distribution in noisy environments. Independent core 10 24 Q9 Q0 11 23 NC NC and output bank supply pins provide integrated level translation without the need for external circuitry. Functional Block Diagram Patents pending Power Vref V Supply REF DIV A Generator Filtering VDDOA SFOUT 1:0 A OE A CLK0 Q0, Q1, Q2, Q3, Q4 DivA CLK0 Q0, Q1, Q2, Q3, Q4 DIV B V DDOB SFOUT 1:0 B OEB Q5, Q6, Q7, Q8, Q9 CLK1 DivB Q5, Q6, Q7, Q8, Q9 CLK1 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021 12 VDD VDDOA 13 NC Q3 14 CLK0 Q3 15 CLK0 Q4 OEA 16 Q4 V 17 REF GND OEB 18 Q5 CLK1 19 Q5 20 CLK1 Q6 21 NC Q6 22 GND V DDOBSi53313 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Functional Description .11 2.1. Universal, Any-Format Input .11 2.2. Input Bias Resistors .13 2.3. Voltage Reference (VREF) 13 2.4. Universal, Any-Format Output Buffer 14 2.5. Flexible Output Divider .15 2.6. Output Enable Logic .15 2.7. Power Supply (VDD and VDDOX) 15 2.8. Output Clock Termination Options 16 2.9. AC Timing Waveforms .19 2.10. Typical Phase Noise Performance .20 2.11. Input Mux Noise Isolation 23 2.12. Power Supply Noise Rejection 23 3. Pin Description: 44-Pin QFN .24 4. Ordering Guide 27 5. Package Outline .28 5.1. 7x7 mm 44-QFN Package Diagram .28 6. PCB Land Pattern 30 6.1. 7x7 mm 44-QFN Package Land Pattern 30 7. Top Marking 31 7.1. Si53313 Top Marking 31 7.2. Top Marking Explanation .31 Document Change List .32 Contact Information 33 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021