Si53314-B-GMR Silicon Labs

25 26 27 28 29 30 31 32 Si53314 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ) Features 6 differential or 12 LVCMOS outputs Independent V and V : DD DDO Ultra-low additive jitter: 45 fs rms 1.8/2.5/3.3 V Wide frequency range: 1.2/1.5 V LVCMOS output support dc to 1.25 GHz Excellent power supply noise Universal input with pin selectable rejection (PSRR) output formats Selectable LVCMOS drive strength to LVPECL, Low Power LVPECL, tailor jitter and EMI performance LVDS, CML, HCSL, LVCMOS Small size: 32-QFN (5x5 mm) 2:1 mux with hot-swappable inputs RoHS compliant, Pb-free Individual output enable Industrial temperature range: 40 to +85 C Ordering Information: Applications See page 27. High-speed clock distribution Storage Ethernet switch/router Telecom Pin Assignments Optical Transport Network (OTN) Industrial SONET/SDH Servers Si53314 PCI Express Gen 1/2/3 Backplane clock distribution Description 24 OE5 OE0 1 23 SFOUTB 1 SFOUTA 1 2 The Si53314 is an ultra low jitter six output differential buffer with pin-selectable 22 SFOUTB 0 SFOUTA 0 3 output clock signal format and individual OE. The Si53314 features a 2:1 mux 21 Q5 4 Q0 GND making it ideal for redundant clocking applications. The Si53314 utilizes Skyworks PAD 20 5 Q5 Q0 Solutions advanced CMOS technology to fanout clocks from dc to 1.25 GHz with VDDOB 19 GND 6 guaranteed low additive jitter, low skew, and low propagation delay variability. The VDDOA 18 VDD 7 Si53314 features minimal cross-talk and provides superior supply noise rejection, 17 VREF CLK SEL 8 simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Patents pending Functional Block Diagram VDD VDDOA Power SFOUT 1:0 Vref A V Supply REF Generator OE 2:0 Filtering CLK0 BANK A /CLK0 VDDO B CLK1 SFOUT 1:0 B OE 5:3 /CLK1 Switching CLK SEL Logic BANK B Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 8, 2021 Q1 OE1 9 Q1 CLK0 10 CLK0 11 Q2 OE Q2 2 12 Q3 OE 13 3 Q3 CLK1 14 15 Q4 CLK1 Q4 16 OE4Si53314 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Functional Description .11 2.1. Universal, Any-Format Input .11 2.2. Input Bias Resistors .13 2.3. Input Clock Voltage Reference (VREF) 13 2.4. Universal, Any-Format Output Buffer 14 2.5. Input Mux and Output Enable Logic .15 2.6. Power Supply (V and V ) 15 DD DDOX 2.7. Output Clock Termination Options 16 2.8. AC Timing Waveforms .19 2.9. Typical Phase Noise Performance 20 2.10. Input Mux Noise Isolation 23 2.11. Power Supply Noise Rejection 23 3. Pin Descriptions .24 4. Ordering Guide 27 5. Package Outline .28 5.1. 5x5 mm 32-QFN Package Diagram .28 6. PCB Land Pattern 29 6.1. 5x5 mm 32-QFN Package Land Pattern 29 7. Top Marking 30 7.1. Si53314 Top Marking 30 7.2. Top Marking Explanation .30 Document Change List .31 Contact Information 32 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 8, 2021