34 35 36 37 38 39 40 41 42 43 44 Si53315 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ) Features 10 differential or 20 LVCMOS outputs Low propagation delay variation: <400 ps Ultra-low additive jitter: 100 fs rms Independent V and V : Wide frequency range: DD DDO 1 MHz to 1.25 GHz 1.8/2.5/3.3 V Any-format input with pin selectable Excellent power supply noise output formats: LVPECL, Low Power rejection (PSRR) LVPECL, LVDS, CML, HCSL, Selectable LVCMOS drive strength to LVCMOS tailor jitter and EMI performance 2:1 mux with hot-swappable inputs Small size: 44-QFN (7 mm x 7 mm) Asynchronous output enable RoHS compliant, Pb-free Individual output enable Industrial temperature range: Ordering Information: Low output-output skew: <50 ps 40 to +85 C See page 25. Applications High-speed clock distribution Storage Pin Assignments Ethernet switch/router Telecom Optical Transport Network (OTN) Industrial Si53315 SONET/SDH Servers PCI Express Gen 1/2/3 Backplane clock distribution Description 1 33 OE2 OE7 SFOUT 0 2 32 SFOUT 1 3 31 OE1 OE8 The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable 4 30 Q2 Q7 output clock signal format and individual OE. The Si53315 features a 2:1 mux, 5 29 Q2 Q7 GND GND 6 28 NC making it ideal for redundant clocking applications. The Si53315 utilizes Skyworks PAD Q1 7 27 Q8 8 Solutions advanced CMOS technology to fanout clocks from 1 MHz to 1.25 GHz Q1 26 Q8 9 25 Q9 Q0 with guaranteed low additive jitter, low skew, and low propagation delay variability. 10 24 Q0 Q9 11 23 OE0 OE9 The Si53315 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Patents pending Functional Block Diagram Power Vref V Supply REF Generator Filtering V DDOA OE 0:4 Q0, Q1, Q2, Q3, Q4 Q0, Q1, Q2, Q3, Q4 CLK0 CLK0 SFOUT 1:0 V DDOB CLK1 OE 5:9 CLK1 Q5, Q6, Q7, Q8, Q9 Switching Q5, Q6, Q7, Q8, Q9 CLK SEL Logic Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.4 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 4, 2021 VDD 12 V DDOA OE3 13 Q3 14 CLK0 Q3 15 CLK0 Q4 16 OE4 Q4 V 17 REF CLK SEL 18 OE5 Q5 19 CLK1 Q5 CLK1 20 Q6 OE6 21 Q6 22 GND V DDOBSi53315 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Functional Description .10 2.1. Universal, Any-Format Input .10 2.2. Input Bias Resistors .12 2.3. Universal, Any-Format Output Buffer 12 2.4. Input Mux and Output Enable Logic .13 2.5. Power Supply (V and V ) 13 DD DDOX 2.6. Output Clock Termination Options 14 2.7. AC Timing Waveforms .17 2.8. Typical Phase Noise Performance 18 2.9. Input Mux Noise Isolation .19 2.10. Power Supply Noise Rejection 20 3. Pin Description: 44-Pin QFN .21 4. Ordering Guide 25 5. Package Outline .26 5.1. 7x7 mm 44-QFN Package Diagram .26 6. PCB Land Pattern 27 6.1. 7x7 mm 44-QFN Package Land Pattern 27 7. Top Marking 28 7.1. Si53315 Top Marking 28 7.2. Top Marking Explanation .28 Contact Information 30 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.4 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 4, 2021