Si5341/40 LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT CLOCK GENERATOR Features Generates free-running or DCO mode with frequency synchronous output clocks increment and decrement as low as 0.001 ppb/step MultiSynth technology enables any-frequency synthesis on any- Core voltage: output with 0 ppm frequency V : 1.8 V 5% DD accuracy with respect to the input V : 3.3 V 5% DDA Highly configurable outputs Independent output supply pins: compatible with LVDS, LVPECL, 3.3V, 2.5V, or 1.8V LVCMOS, HCSL, or programmable Ordering Information: Built-in power supply filtering voltage swing and common mode See section 7 Status monitoring: LOS, LOL Excellent jitter: <100 fs RMS typ 2 Serial Interface: I C or SPI (3-wire Input frequency range: or 4-wire) External crystal: 25, 48-54 MHz Pin Assignments In-circuit programmable with non- Differential clock: 10 to 750 MHz volatile OTP memory (2x LVCMOS clock: 10 to 250 MHz Si5341 64QFN programmable) Top View Output frequency range: TM ClockBuilder Pro software utility Differential: 100 Hz to 800 MHz simplifies device configuration and LVCMOS: 100 Hz to 250 MHz assigns customer part numbers IN1 1 48 FINC Output-output skew: <100 ps 47 IN1 2 LOL Si5341: 4 input, 10 output, 64 QFN IN SEL0 3 46 VDD Adjustable output-output delay IN SEL1 4 45 OUT6 Si5340: 4 input, 4 output, 44 QFN SYNC 5 44 OUT6 Optional zero delay mode RST 6 43 VDDO6 Temperature range: 40 to +85 C X1 7 42 OUT5 Independent glitchless on-the-fly XA 8 GND 41 OUT5 Pb-free, RoHS-6 compliant output frequency changes XB 9 40 VDDO5 Pad X2 10 39 I2C SEL OE 11 38 OUT4 Applications INTR 12 37 OUT4 13 36 VDDA VDDO4 IN2 14 35 OUT3 Clock tree generation replacing Ethernet switches/routers 15 34 IN2 OUT3 SCLK 16 33 VDDO3 XOs, buffers, signal format OTN framers/mappers/processors translators Test equipment & instrumentation Any-frequency synchronous clock Broadcast video translation Si5340 44QFN Clocking for FPGAs, processors, Top View memory Description The any-frequency, any-output Si5341/40 clock generators combine a wide-band IN1 1 33 INTR PLL with proprietary MultiSynth fractional synthesizer technology to offer a 2 32 IN1 VDD IN SEL0 3 31 OUT2 versatile and high performance clock generator platform. This highly flexible 4 30 OUT2 X1 architecture is capable of synthesizing a wide range of integer and non-integer XA 5 29 VDDO2 GND related frequencies up to 800MHz on 10 differential clock outputs while 6 28 LOS XAXB XB Pad 7 27 LOL X2 delivering sub-100 fs rms phase jitter performance and 0 ppm error. Each of the VDDA 8 26 VDDS clock outputs can be assigned its own format and output voltage enabling the OUT1 VDDA 9 25 10 24 OUT1 IN2 Si5341/40 to replace multiple clock ICs and oscillators with a single device 11 23 VDDO1 IN2 making it a true clock tree in a chip. The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software. Custom part numbers are automatically assigned using a ClockBuilderPro for fast, free, and easy factory programming, or the Si5341/40 2 can be programmed in-circuit via I C and SPI serial interface. Preliminary Rev. 0.9 7/14 Copyright 2014 by Silicon Laboratories Si5341/40 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. 17 A1/SDO 64 IN0 12 44 SDA/SDIO 18 63 IN0 OE IN0 19 A0/CS 62 FB IN SDA/SDIO 13 43 IN0 20 61 FB IN RSVD SCLK 14 42 FB IN RSVD 21 60 VDD A1/SDO 15 41 FB IN 22 59 OUT9 VDDO0 16 A0/CS 40 VDD 23 OUT0 58 OUT9 17 39 24 57 VDDO9 RST VDD OUT0 25 FDEC 56 RSVD 18 38 VDDO0 I2C SEL 26 55 VDDO1 RSVD OUT0 19 37 IN SEL1 27 54 OUT8 OUT1 20 OUT0 36 OUT3 28 53 OUT8 OUT1 21 35 VDD OUT3 VDDO2 29 52 VDDO8 22 34 VDDO3 30 51 OUT7 NC OUT2 OUT2 31 50 OUT7 32 49 VDDO7 VDDSi5341 Si5340 Si5341/40 Functional Block Diagram Si5341/40 IN SEL IN0 INT INT IN1 INT IN2 PLL XA OSC XB INT FB IN Multi INT OUT0 Synth Multi INT OUT1 Synth Multi INT OUT2 Synth Multi INT OUT3 Synth Multi INT OUT4 Synth INT OUT5 INT OUT6 NVM 2 I C/SPI INT OUT7 Control/ INT OUT8 Status INT OUT9 2 Preliminary Rev. 0.9 XTAL