Si5356A 2 I C PROGRAMMABLE, ANY-FREQUENCY 1200 MHZ, QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR Features Generates any frequency from 1 to OEB pin disables all outputs or per 2 200 MHz on each of the 4 output banks bank OEB control via I C Programmable frequency configuration Low jitter: 50 ps pk-pk (typ), 75 ps Guaranteed 0 ppm frequency synthesis pk-pk period jitter (max) error for any combination of frequencies Excellent PSRR performance 25 or 27 MHz xtal or 5200 MHz input clk eliminates need for external power Eight CMOS clock outputs supply filtering Easy to use programming software Low power: 45 mA (core) Configurable triple A spread spectrum: Core VDD: 1.8, 2.5, or 3.3 V Ordering Information: any clock, any frequency, and with any Separate VDDO for each bank of See page 23. spread amount outputs: 1.8, 2.5, or 3.3 V Programmable output phase adjustment Small size: 4x4 mm 24-QFN with <20 ps error Industrial temperature range: Pin Assignments Interrupt pin indicates LOS or LOL 40 to +85 C Applications Top VieTop Vieww Printers Storage area networks Audio/video Switches/routers DSLAM Servers 2424 2323 2222 2121 2020 1919 1818 XAXA1 1 CLCLKK22 Description 1717 XBXB2 2 CLCLKK33 2 The Si5356 is a highly flexible, I C programmable clock generator capable of 1616 I2C LSP1 B3 3 VVDDDDOBOB synthesizing four completely non-integer related frequencies up to 200 MHz. The GNDGNDGNDGND 1515 device has four banks of outputs with each bank supporting two CMOS outputs at CLCLKINKIN4 4 VDVDDDOOCC the same frequency. Using Silicon Laboratories patented MultiSynth fractional 1414 SSCP4 DIS5 5 CLCLKK44 divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis OEB6 6 1313 CLK5 P5 CLK5 error regardless of configuration, enabling the replacement of multiple clock ICs 71718 8 9 9 1010 111122 and crystal oscillators with a single device. Each output bank is independently 2 configurable to support 1.8, 2.5, or 3.3 V. The device is programmable via an I C/ SMBus-compatible serial interface and supports operation from a 1.8, 2.5, or 3.3 V core supply. Functional Block Diagram Rev. 1.3 Copyright 2014 by Silicon Laboratories Si5356A VDD VDD VDD VDD LOS GND INTR GND CLK7 CLK0 CLK7 CLK0 CLK6 CLK1 CLK6 CLK1 VDDOD VDDOD VDDOA VDDOA P2 SCL P3 SDASi5356A 2 Rev. 1.3