SI5364-H-GL Silicon Labs

Si5364 SONET/SDH PRECISION PORT CARD CLOCK IC Features Ultra-low jitter clock outputs with jitter Automatic or manually-controlled hitless generation as low as 0.3 ps switching between clock inputs RMS Revertive/non-revertive switching No external components (other than a resistor and standard bypassing) Loss-of-signal and frequency offset alarms for each clock input Up to three clock inputs Support for forward and reverse FEC Four independent clock outputs at 19, Si5364 clock scaling 155, or 622 MHz 8 kHz frame sync output Stratum 3, 3E, and SMC compatible Low power Digital hold for loss-of-input clock Small size (11x11 mm) Bottom View Applications Ordering Information: SONET/SDH line/port cards Core switches See page 34. Terabit routers Digital cross connects Description The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/ port cards. This device phase locks to one of three reference inputs in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock). Silicon Laboratories DSPLL technology delivers phase-locked loop (PLL) functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. The on-chip reference monitoring and clock switching functions support Stratum 3/3E and SMC compatible clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios. The Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram REXT VSEL33 VDD GND FEC 1:0 BWSEL 1:0 2 2 Biasing & Supply CAL ACTV CLKIN A+ 2 CLKOUT 1+ CLKIN A CLKOUT 1 2 2 TM CLKIN B+ SiLECT FRQSEL 1 1:0 TM DSPLL CLKIN B Switching CLKOUT 2+ 2 CLKOUT 2 REF/CLKIN F+ 2 REF/CLKIN F FRQSEL 2 1:0 LOS A FOS A CLKOUT 3+ LOS B CLKOUT 3 2 FOS B FRQSEL 3 1:0 LOS F CLKOUT 4+ DSBLFOS Signal CLKOUT 4 Detection, SMC/S3N 2 Selection, VALTIME FRQSEL 4 1:0 & Control AUTOSEL RVRT FSYNC MANCNTRL 1:0 DSBLFSYNC INCDELAY DECDELAY SYNCIN FXDDELAY A ACTV DH ACTV B ACTV RSTN/CAL F ACTV Rev. 2.5 8/08 Copyright 2008 by Silicon Laboratories Si5064Si5364 2 Rev. 2.5