Si5369 ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Generates any frequency from 2 kHz Five clock outputs with selectable to 945 MHz and select frequencies to signal format (LVPECL, LVDS, CML, 1.4 GHz from an input frequency of CMOS) 2 kHz to 710 MHz Support for ITU G.709 and custom Ultra-low jitter clock outputs with jitter FEC ratios (253/226, 239/237, generation as low as 300 fs rms 255/238, 255/237, 255/236) (12 kHz20 MHz) LOL, LOS, FOS alarm outputs Integrated loop filter with selectable Digitally-controlled output phase loop bandwidth (4 Hz to 525 Hz) adjust Ordering Information: Meets OC-192 GR-253-CORE jitter 2 I C or SPI programmable settings See page 78. specifications On-chip voltage regulator for 1.8 V Four clock inputs with manual or 5%, 2.5 V 10%, or 3.3 V 10% automatically controlled hitless operation switching and phase build-out Small size: 14 x 14 mm 100-pin Supports holdover and freerun TQFP modes of operation Pb-free, RoHS compliant SONET frame sync switching and regeneration Applications SONET/SDH OC-48/STM-16/OC- OTN/WDM Muxponder, MSPP, 192/STM-64 line cards ROADM line cards GbE/10GbE, 1/2/4/8/10G FC line cards SONET/SDH + PDH clock ITU G.709 and custom FEC line cards synthesis Wireless repeaters/wireless backhaul Test and measurement Data converter clocking Synchronous Ethernet Broadcast video Description The Si5369 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5369 input clock frequency and clock 2 multiplication ratio are programmable through an I C or SPI interface. The Si5369 is based on Skyworks Solutions third-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5369 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 1, 2021Si5369 Functional Block Diagram Xtal or Refclock CKIN1 N31 CKIN2 N32 NC1 LS CKOUT1 N1 HS DSPLL CKIN3/FSYNC1 N33 NC2 LS CKOUT2 CKIN4 N34 N2 NC3 LS CKOUT3 2 I C/SPI Port NC4 LS CKOUT4 Rate Select Clock Select Control Skew Control NC5 LS CKOUT5 Device Interrupt VDD (1.8, 2.5, or 3.3 V) LOL/LOS/FOS Alarms GND 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.0 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 1, 2021