Si5380 Rev D Data Sheet 12 Output JESD204B Wireless Jitter Attenuator/ Clock Multiplex- KEY FEATURES or with Ultra-low Phase Noise DSPLL eliminates external VCXO and The Si5380 is a high performance, integer-based (M/N) jitter attenuator for small cell analog loop filter components applications which demand the highest level of integration and phase noise perform- Supports JESD204B clocking: DCLK and th ance. Based on Skyworks Solutions 4 generation DSPLL technology, the Si5380 SYSREF combines frequency synthesis and jitter attenuation in a highly integrated digital solu- Ultra-low jitter of 65 fs tion that eliminates the need for external VCXO and loop filter components. The fixed Input frequency range: frequency oscillator provides frequency stability for free-run and holdover modes. This Differential: 11.52 MHz to 737.28 MHz all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. LVCMOS: 11.52 MHz to 245.76 MHz Output frequency range: Differential: 480 kHz to 1.47456 GHz Applications: LVCMOS: 480 kHz to 245.76 MHz JESD204B clock generation Status monitoring Hitless switching Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells Si5380: 4 input, 12 output, 64-QFN 99 mm Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) Remote Radio Head (RRH), wireless repeaters, wireless backhaul Data conversion sampling clocks (ADC, DAC, DDC, DUC) 54 MHz XTAL XA XB INT OUT0A OSC INT OUT0 INT N IN0 INT INT OUT1 INT OUT2 INT DSPLL IN1 INT N 4 Input INT OUT3 Clocks INT IN2 INT OUT4 INT N Device and INT OUT5 IN3/FB IN INT System Clocks INT OUT6 INT N INT OUT7 OUT8 INT Status Flags Status Monitor INT N INT OUT9 I2C / SPI Control NVM OUT9A INT Si5380 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 22, 2021 1 Not Recommended for New DesignsTable of Contents 1. Feature List................................4 2. Ordering Guide ..............................5 3. Functional Description............................6 3.1 Frequency Configuration ..........................6 3.1.1 Si5380 LTE Frequency Configuration.....................6 3.1.2 Si5380 Configuration for JESD204B Clock Generation...............7 3.1.3 DSPLL Loop Bandwidth .........................7 3.1.4 Fastlock...............................7 3.1.5 Modes of Operation...........................8 3.1.6 Initialization and Reset..........................8 3.1.7 Freerun Mode.............................8 3.1.8 Lock Acquisition............................8 3.1.9 Locked Mode.............................9 3.1.10 Holdover Mode............................9 3.2 External Reference (XA/XB) .........................10 3.3 Inputs (IN0, IN1, IN2, IN3/FB IN)........................10 3.3.1 Input Configuration and Terminations.....................11 3.3.2 Manual Input Selection (IN0, IN1, IN2, IN3/FB IN) ................12 3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB IN) ...............12 3.3.4 Hitless Input Switching..........................12 3.3.5 Ramped Input Switching .........................12 3.3.6 Glitchless Input Switching.........................12 3.3.7 Zero Delay Mode............................13 3.4 Fault Monitoring .............................14 3.4.1 Input LOS Detection...........................14 3.4.2 XA/XB LOS Detection..........................14 3.4.3 OOF Detection ............................15 3.4.4 Precision OOF Monitor..........................15 3.4.5 Fast OOF Monitor ...........................15 3.4.6 LOL Detection.............................16 3.4.7 Interrupt Pin INTRb...........................17 3.5 Outputs ................................17 3.5.1 Output Crosspoint ...........................17 3.5.2 Output Signal Format ..........................17 3.5.3 Output Terminations...........................18 3.5.4 Programmable Common Mode Voltage For Differential Outputs............18 3.5.5 LVCMOS Output Terminations .......................19 3.5.6 LVCMOS Output Impedance and Drive Strength Selection..............19 3.5.7 LVCMOS Output Signal Swing .......................19 3.5.8 LVCMOS Output Polarity.........................19 3.5.9 Output Enable/Disable..........................19 3.5.10 Output Disable During LOL........................19 3.5.11 Output Disable During XAXB LOS .....................20 3.5.12 Output Driver State When Disabled.....................20 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 22, 2021 2 Not Recommended for New Designs