Si8430/31/35 LOW-POWER TRIPLE-CHANNEL DIGITAL ISOLATOR Features High-speed operation Up to 2500 V isolation RMS DC to 150 Mbps 60-year life at rated working No start-up initialization required voltage Wide Operating Supply Voltage: Precise timing (typical) 2.705.5 V <10 ns worst case Wide Operating Supply Voltage: 1.5 ns pulse width distortion 2.705.5V 0.5 ns channel-channel skew 2 ns propagation delay skew Ultra low power (typical) 6 ns minimum pulse width 5 V Operation: Transient Immunity 25 kV/s < 1.6 mA per channel at 1 Mbps < 6 mA per channel at 100 Mbps AEC-Q100 qualified 2.70 V Operation: Wide temperature range < 1.4 mA per channel at 1 Mbps 40 to 125 C at 150 Mbps < 4 mA per channel at 100 Mbps RoHS-compliant packages High electromagnetic immunity SOIC-16 wide body SOIC-16 narrow body Applications Industrial automation systems Isolated ADC, DAC Hybrid electric vehicles Motor control Ordering Information: Isolated switch mode supplies Power inverters See page 26. Communications systems Safety Regulatory Approvals UL 1577 recognized VDE certification conformity Up to 2500 V for 1 minute IEC 60747-5-2 RMS (VDE0884 Part 2) CSA component notice 5A approval IEC 60950-1, 61010-1 (reinforced insulation) Description Silicon Lab s family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life, and only VDD bypass capacitors are required. Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. All products are safety certified by UL, CSA, and VDE and support withstand voltages of up to 2.5 kV . These devices are available in 16-pin wide- and RMS narrow-body SOIC packages. Rev. 1.7 4/18 Copyright 2018 by Silicon Laboratories Si8430/31/35 Not Recommended for New DesignsSi8430/31/35 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Functional Description .17 2.1. Theory of Operation .17 2.2. Eye Diagram .18 2.3. Device Operation .19 2.4. Layout Recommendations 21 2.5. Typical Performance Characteristics 22 3. Errata and Design Migration Guidelines .24 3.1. Enable Pin Causes Outputs to Go Low (Revision C Only) 24 3.2. Power Supply Bypass Capacitors (Revision C and Revision D) 24 3.3. Latch Up Immunity (Revision C Only) 24 4. Pin Descriptions .25 5. Ordering Guide 26 6. Package Outline: 16-Pin Wide Body SOIC 28 7. Land Pattern: 16-Pin Wide-Body SOIC .29 8. Package Outline: 16-Pin Narrow Body SOIC 30 9. Land Pattern: 16-Pin Narrow Body SOIC .32 10. Top Marking: 16-Pin Wide Body SOIC 33 10.1. 16-Pin Wide Body SOIC Top Marking .33 10.2. Top Marking Explanation 33 11. Top Marking: 16-Pin Narrow Body SOIC 34 11.1. 16-Pin Narrow Body SOIC Top Marking .34 11.2. Top Marking Explanation 34 Document Change List .35 Rev. 1.7 2 Not Recommended for New Designs