SL16020DC Low Jitter and Power Clock Generator with SSCG Key Features Description The SL16020DC is a low power dissipation spread Low power dissipation spectrum clock generator using SLI proprietary low jitter - 14.5mA-typ CL=15pF PLL. The SL16020DC provides two output clocks. - 20.0mA-max CL=15pF REFCLK (Pin-9) which is a buffered output of the 3.3V +/-10% power supply range 27.000MHz input crystal and SSCLK (Pin-5) which is 27.000MHz crystal or clock input synthesized as 100.000MHz nominal by an internal PLL 27.000MHz REFCLK using the 27.00MHz external input crystal or clock. 100MHz SSCLK with SSEL0/1 spread options In addition, SSEL0 (Pin-7) and SSEL1 (Pin-3) spread Low CCJ Jitter percent selection control inputs enable users to select Low LT Jitter from 0.0% (no spread) to 1.5% down spread at Internal Voltage Regulators 100.000MHz SSCLK output to reduce and optimize 45% to 55% Output Duty Cycle system EMI levels. On-chip Crystal Oscillator -10 to +85 Temperature Range The SL16020DC operates in an extended temperature 10-pin 3x3x0.75 mm TDFN package range of -10 to +85C. Application Contact SLI for other programmable frequencies, Spread Spectrum Clock (SSC) options, as well as 2.5V+/-10 and Video Cards 1.8V+/-5% power supply options. NB and DT PCs HDTV and DVD-R/W Benefits Routers, Switches and Servers EMI Reduction Data Communications Improved Jitter Embeded Digital Applications Low Power Dissipation Eleminates external Xtals or XOs Block Diagram REFCLK 9 27.000MHz 300K Low Jitter PLL SSCLK XIN/CLKIN 5 1 With 100.000MHz Modulation Control With Spread Options XOUT 10 Input Decoder 4 6 8 2 7 3 VDD1 VSS1 VDD2 VSS2 SSEL0 SSEL1 Figure 1. Block Diagram Rev 2.2, August 1, 2010 Page 1 of 10 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL16020DC Pin Configuration XIN/CLKIN 1 10 XOUT 2 9 REFCLK VSS2 3 8 VDD2 SSEL1 VDD1 7 4 SSEL0 5 SSCLK 6 VSS1 Figure 2. 10-Pin TDFN (3x3x0.75 mm) Table 1. Pin Description Pin Pin Name Pin Type Pin Description Number 1 XIN Input External crystal or clock input. Capacitance at this pin is 4 pF-typ. 2 VSS2 Power Power supply ground for 27.000MHz REFCLK output. 3 SSEL1 Input SSEL1 spread percent selection pin. Refer to Table 5 for available spread options using SSEL1 pin. This pin has 150k pull down resistor to VSS. 4 VDD1 Power Positive power supply for 100.000MHz SSCLK output. 3.3V +/-10%. 5 SSCLK Output SSCLK clock output. 100.000MHz nominal. Refer to Table 5 for available spread % options by using SSEL0 and SSEL1 control pins. 6 VSS1 Power Power supply ground for 100.000MHz SSCLK output. 7 SSEL0 Input SSEL spread percent selection pin. Refer to Table 5 for available spread options using SSEL0 pin. This pin has 150k pull down resistor to VSS. 8 VDD2 Power Positive power supply for 27.000MHz REFCLK output. 3.3V +/-10%. 9 REFCLK Output REFCLK clock output. 27.000MHz nominal. 10 XOUT Output Crystal output. Capacitance at this pin 4 pF-typ. If clock input is used, leave this pin unconnected (N/C). Rev 2.2, August 1, 2010 Page 2 of 10