SL28610 Low Power Clock Generator for Intel Ultra Mobile Platform Features Supports intel s Moorestown and Menlow clocking Buffered Reference Clock 14.318MHz requirements 14.318 MHz Crystal Input or Clock Input Compliant to Intel CK610 Low-voltage frequency select input Low power push-pull type differential output buffers 2 I C support with readback capabilities Integrated voltage regulator Triangular Spread Spectrum profile for maximum Integrated resistors on differential clocks electromagnetic interference (EMI) reduction Differential CPU clocks with selectable frequency Industrial Temperature -40C to 85C 100MHz Differential PCIe clocks 48-pin QFN package 100MHz LCD Video Clock 96MHz Differential DOT clock CPU PCIe DOT96 LCD REF x3 x3 x 1 x1 x 1 Block Diagram Pin Configuration * 100K-ohm Internal pull down ** 10K-ohm Internal pull-up ........................ DOC : SP-AP-0078 (Rev. 1.0) Page 1 of 23 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL28610 Pin Definitions Pin No. Name Type Description 1 CPU STP I, SE 3.3V input for CPU STP (active low) functionality 2 CKPWRGD /PD I, SE 3.3V LVTTL input (active low) 3 XOUT O, SE 3.3V, 14.31818MHz crystal output (When used a clock input, float XOUT) 4 XIN/CLKIN I, SE 3.3V, 14.31818MHz crystal input, 3.3V Clock Input. 5 VDD3.3V PWR 3.3V power supply for single-ended clock 6 REF / PCIe SEL IO, PD, 3.3V, 14.31818MHz output / 1.5V input active high signal latched on CKPWRGD SE signal to select PCIe from PLL3 (share with LCD PLL 100K-ohm internal pull-down) 7 VSS GND Ground 8 VDD1.5 CORE PWR 1.5V power supply for core 9 FSC I, SE 1.05V Frequency Select C 10 TEST MODE I, SE 3.3V-tolerant input to selects Ref/N or Tri-state when in test mode. 0 = Tri-state, 1 = Ref/N 11 TEST SEL I, SE 3.3V-tolerant input to selects TEST SEL 0 = Normal, 1 = Test Entry 12 SCLK I, SE 3.3V SMBus Clock Line 13 SDATA I/O, SE 3.3V SMBus Data Line 14 VDD1.5 CORE PWR 1.5V power supply for core 15 VDD1.5 IO PWR 1.5V power supply for differential outputs 16 DOT96 O, DIFF Fixed complimentary 96MHz clock output 17 DOT96 O, DIFF Fixed true 96MHz clock output 18 VSS GND Ground 19 VSS GND Ground 20 LCD SSC O, DIF Complementary 100MHz Differential clock 21 LCD SSC O, DIF True 100MHz Differential clock 22 VDD1.5 IO PWR 1.5V power supply for differential outputs 23 VDD1.5 CORE PWR 1.5V power supply for core 24 OE 0 I, SE Output enable for PCIe0, (10K-ohm internal pull-up) 0 =enable, 1=disable 25 VSS GND Ground 26 PCIe0 O, DIF Complementary 100MHz Differential clock 27 PCIe0 O, DIF True 100MHz Differential clock 28 OE 1 I, SE Output enable for PCIe1, (10K-ohm internal pull-up) 0 =enable, 1=disable 29 VDD1.5 CORE PWR 1.5V Power Supply for core 30 VDD1.5 IO PWR 1.5V Power Supply for differential output 31 PCIe1 O, DIF Complementary 100MHz Differential clock 32 PCIe1 O, DIF True 100MHz Differential clock 33 VSS GND Ground 34 PCIe2 O, DIF Complementary 100MHz Differential clock 35 PCIe2 O, DIF True 100MHz Differential clock 36 OE 2 I, SE Output enable for PCIe2, (10K-ohm internal pull-up) 0 =enable, 1=disable 37 FSB I, SE 1.05V Frequency Select B 38 CPU0 O, DIF Complementary Host Differential clock 39 CPU0 O, DIF True Host Differential clock ........................DOC : SP-AP-0078 (Rev. 1.0) Page 2 of 23