W134 Direct Rambus Clock Generator Features Description Differential clock source for Direct Rambus memory The Cypress W134M/W134S provides the differential clock subsystem for up to 800-MHz data transfer rate signals for a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an Provide synchronization flexibility: the Rambus external system clock but can also be used in systems that do Channel can optionally be synchronous to an external not require synchronization of the Rambus clock. system or processor clock Power-managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications Works with Cypress CY2210, W133, W158, W159, W161, and W167 to support Intel architecture platforms Low-power CMOS design packaged in a 24-pin QSOP (150-mil SSOP) package Block Diagram Pin Configuration REFCLK VDDIR 1 24 S0 PLL MULT0:1 REFCLK 2 23 S1 VDD 3 22 VDD GND 4 21 GND GND 5 20 CLK PCLKM 6 19 NC SYNCLKN 7 18 CLKB CLK Output Phase PCLKM GND 8 17 GND Logic CLKB Alignment VDD 9 16 VDD SYNCLKN VDDIPD 10 15 MULT0 STOPB 11 14 MULT1 PWRDNB 12 13 GND Test S0:1 Logic STOPB ........................ Document : 38-07426 Rev. *C Page 1 of 11 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com W134 Pin Definitions Pin Name No. Type Description REFCLK 2 I Reference Clock Input. Reference clock input, normally supplied by a system frequency synthesizer (Cypress W133). PCLKM 6 I Phase Detector Input. The phase difference between this signal and SYNCLKN is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground. SYNCLKN 7 I Phase Detector Input. The phase difference between this signal and PCLKM is used to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio Logic is not used, this pin would be connected to Ground. STOPB 11 I Clock Output Enable. When this input is driven to active LOW, it disables the differential Rambus Channel clocks. PWRDNB 12 I Active LOW Power-down. When this input is driven to active LOW, it disables the differ- ential Rambus Channel clocks and places the W134M/W134S in power-down mode. MULT 0:1 15, 14 I PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to determine the multiply ratio for the PLL for the input REFCLK. W134S W134M PLL/REFCLK MULT0 MULT1 PLL/REFCLK 4 0 0 4.5 6 0 1 6 8 1 1 8 5.333 1 0 5.333 CLK, CLKB 20, 18 O Complementary Output Clock. Differential Rambus Channel clock outputs. S0, S1 24, 23 I Mode Control Input. These inputs control the operating mode of the W134M/W134S. S0 S1 MODE 0 0 Normal 0 1 Output Enable Test 1 0 Bypass 1 1 Test NC 19 No Connect VDDIR 1 RefV Reference for REFCLK. Voltage reference for input reference clock. VDDIPD 10 RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB. VDD 3, 9, 16, 22 P Power Connection. Power supply for core logic and output buffers. Connected to 3.3V supply. GND 4, 5, 8, 13, 17, G Ground Connection. Connect all ground pins to the common system ground plane. 21 W134M/W134S W133 W158 Refclk Phase W159 PLL Busclk Align W161 W167 D CY2210 RAC RMC M N 4 DLL Pclk Synclk Gear Ratio Logic Figure 1. DDLL System Architecture ........................Document : 38-07426 Rev. *C Page 2 of 11 Pclk/M Synclk/N