SiT1552 2 Smallest (1.2 mm ), Ultra-Low Power, 32.768 kHz MEMS TCXO 2 Smallest (1.2mm ), Ultra-Low Power, 32.768 kHz MEMS TCXO Features Applications 32.768 kHz 5, 10, 20 ppm frequency stability options Smart Meters (AMR) over temp Health and Wellness Monitors Worlds smallest TCXO in a 1.5 x 0.8 mm CSP Pulse-per-Second (pps) Timekeeping Operating temperature ranges: RTC Reference Clock 0C to +70C -40C to +85C Ultra-low power: <1 A Vdd supply range: 1.5 V to 3.63 V Improved stability reduces system power with fewer network timekeeping updates Internal filtering eliminates external Vdd bypass cap and saves space Pb-free, RoHS and REACH compliant Electrical Specifications Table 1. Electrical Characteristics Parameter Symbol Min. Typ. Max. Unit Condition Frequency and Stability Output Frequency Fout 32.768 kHz Frequency Stability Over -5.0 5.0 ppm Stability part number code = E 1 Temperature F stab 2 -10 10 Stability part number code = F (without Initial Offset ) -20 20 Stability part number code = 1 Frequency Stability Over -10 10 ppm Stability part number code = E Temperature F stab 2 -13 13 Stability part number code = F (with Initial Offset ) -22 22 Stability part number code = 1 Frequency Stability vs Voltage -0.75 0.75 ppm 1.8 V 10% F vdd -1.5 1.5 ppm 1.5 V 3.63 V First Year Frequency Aging F aging -1.0 1.0 ppm T = 25C, Vdd = 3.3 V A Jitter Performance (T = over temp) A Long Term Jitter 2.5 s 81920 cycles (2.5 sec), 100 samples pp Period Jitter 35 ns Cycles = 10,000, T = 25C, Vdd = 1.5 V 3.63 V RMS A Supply Voltage and Current Consumption Operating Supply Voltage Vdd 1.5 3.63 V T = -40C to +85C A 3 Core Supply Current 0.99 A T = 25C, Vdd = 1.8 V, LVCMOS Output configuration, No Load A Idd 1.52 T = -40C to +85C, Vdd = 1.5 V 3.63 V, No Load A t Vdd Power-Supply Ramp 100 ms Vdd Ramp-Up 0 to 90% Vdd, T = -40C to +85C A Ramp Start-up Time at Power-up 180 300 ms T = -40C +60C, valid output A 350 T = +60C to +70C, valid output A t start 380 T = +70C to +85C, valid output A Notes: 1. No board level underfill. Measured as peak-to-peak/2. Inclusive of 3x-reflow and 20% load variation. Tested with Agilent 53132A frequency counter. Due to the low operating frequency, the gate time must be 100 ms to ensure an accurate frequency measurement. 2. Initial offset is defined as the frequency deviation from the ideal 32.768 kHz at room temperature, post reflow. 3. Core operating current does not include output driver operating current or load current. To derive total operating current (no load), add core operating current + output driver operating current, which is a function of the output voltage swing. See the description titled Calculating Load Current. Rev 1.41 November 23, 2020 www.sitime.com 2 SiT1552 Smallest (1.2 mm ), Ultra-Low Power, 32.768 kHz MEMS TCXO Table 1. Electrical Characteristics (continued) Parameter Symbol Min. Typ. Max. Unit Condition Operating Temperature Range Commercial Temperature Op Temp 0 70 C Industrial Temperature -40 85 C LVCMOS Output Output Rise/Fall Time tr, tf 100 200 ns 10-90% (Vdd), 15 pF Load 50 10-90% (Vdd), 5 pF Load, Vdd 1.62 V Output Clock Duty Cycle DC 48 52 % Output Voltage High VOH 90% V Vdd: 1.5 V 3.63 V. I = -1 A, 15 pF Load OH Output Voltage Low VOL 10% V Vdd: 1.5 V 3.63 V. I = 1 A, 15 pF Load OL NanoDrive Programmable, Reduced Swing Output Output Rise/Fall Time tf, tf 200 ns 30-70% (V /V ), 10 pF Load OL OH Output Clock Duty Cycle DC 48 52 % AC-coupled Programmable V sw 0.20 to V SiT1552 does not internally AC-couple. This output description Output Swing 0.80 is intended for a receiver that is AC-coupled. See Table 4 for acceptable NanoDrive swing options. Vdd: 1.5 V 3.63 V, 10 pF Load, I / I = 0.2 A OH OL DC-Biased Programmable VOH 0.60 to V Vdd: 1.5 V 3.63 V. I = -0.2 A, 10 pF Load. See Table 4 for OH Output Voltage High Range acceptable V /V setting levels. 1.225 OH OL DC-Biased Programmable VOL 0.35 to V Vdd: 1.5 V 3.63 V. I = 0.2 A, 10 pF Load. See Table 4 for OL Output Voltage Low Range acceptable V /V setting levels. 0.80 OH OL Programmable Output -0.055 0.055 V T = -40C to +85C, Vdd = 1.5 V to 3.63 V A Voltage Swing Tolerance Table 2. Pin Configuration CSP Pin Symbol I/O Functionality CSP Package (Top View) Connect to ground. All GND pins must be connected to power supply Power ground. The GND pins can be connected together, as long as both GND 1, 4 GND Supply Ground pins are connected ground. GND 1 4 GND Oscillator clock output. When interfacing to an MCUs XTAL, the CLK Out is typically connected to the receiving ICs X IN pin. The SIT1552 oscillator output includes an internal driver. As a result, the output swing and 2 CLK Out OUT operation is not dependent on capacitive loading. This makes the output much more flexible, layout independent, and robust under changing CLK Out 3 Vdd 2 environmental and manufacturing conditions. Connect to power supply 1.5 V Vdd 3.63 V. Under normal operating conditions, Vdd does not require external bypass/decoupling capacitor(s). Figure 1. Pin Assignments For more information about the internal power-supply filtering, Power 3 Vdd Supply see Power-Supply Noise Immunity section in the detailed description. Contact SiTime for applications that require a wider operating supply voltage range. Rev 1.41 Page 2 of 12 www.sitime.com