74VHC238 3 TO 8 LINE DECODER HIGH SPEED: t = 5.5 ns (TYP.) at V = 5V PD CC LOW POWER DISSIPATION: I = 4 A (MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28% V (MIN.) NIH NIL CC POWER DOWN PROTECTION ON INPUTS SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 8 mA (MIN) OH OL BALANCED PROPAGATION DELAYS: Table 1: Order Codes t t PLH PHL OPERATING VOLTAGE RANGE: PACKAGE T & R V (OPR) = 2V to 5.5V CC SOP 74VHC238MTR PIN AND FUNCTION COMPATIBLE WITH TSSOP 74VHC238TTR 74 SERIES 238 IMPROVED LATCH-UP IMMUNITY Tree enable inputs are provided to ease cascade DESCRIPTION connection and application of address decoders for memory systems. The 74VHC238 is an advanced high-speed Power down protection is provided on all inputs CMOS 3 TO 8 LINE DECODER fabricated with and 0 to 7V can be accepted on inputs with no sub-micron silicon gate and double-layer metal 2 regard to the supply voltage. This device can be wiring C MOS technology. used to interface 5V to 3V. If the device is enabled, 3 binary select inputs (A, All inputs and outputs are equipped with B, and C) determine which one of the outputs will protection circuits against static discharge, giving go high. If enable input G1 is held low or either them 2KV ESD immunity and transient excess G2A or G2B is held high, decoding function is voltage. inhibited and all the 8 outputs go to low. Figure 1: Pin Connection And IEC Logic Symbols Rev. 4 November 2004 1/12 Obsolete Product(s) - Obsolete Product(s)74VHC238 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N SYMBOL NAME AND FUNCTION 1, 2, 3 A, B, C Address Inputs 4, 5 G2A, G2B Enable Inputs 6 G1 Enable Input 15, 14, 13, Y0 to Y7 Outputs 12, 11, 10, 9, 7 8 GND Ground (0V) 16 V Positive Supply Voltage CC Table 3: Truth Table INPUTS OUTPUTS ENABLE SELECT G2B G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X X X LLLLLLLL X H XXXX LLLLLLLL H XXXXX LLLLLLLL LL H LLL H LLLLLLL LL H L L H L H LLLLLL LL H L H L LL H LLLLL LL H L H H LLL H LLLL LL H H LL LLLL H LLL LL H H L H LLLLL H L L LL H H H L LLLLLL H L L L HHHH LLLLLLL H X : Dont care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/12 Obsolete Product(s) - Obsolete Product(s)