EMIF10-COM01F2 STMicroelectronics

EMIF10-COM01F2 10-line IPAD, EMI filter including ESD protection Features EMI symmetrical (I/O) low-pass filter Lead free package 2 Very low PCB space consuming: < 6 mm Very thin package: 0.65 mm High efficiency in ESD suppression on both input & output pins Flip Chip High reliability offered by monolithic integration (25 bumps) Complies with the following standard: Figure 1. Pin configuration (bump side) IEC 61000-4-2 level 4 3 54 21 15 kV (air discharge) I5 I4 I3 I2 I1 A 8 kV (contact discharge) I10 I9 I8 I7 I6 B Applications GND GND GND GND GND C EMI filtering and ESD protection for: Computers and printers 010 09 08 07 06 D Communication systems 05 04 03 02 01 E Mobile phones Description Figure 2. Basic cell configuration The EMIF10-COM01F2 is a highly integrated Low-pass Filter device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic Input Output interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size. Additionally, this filter includes an ESD protection circuitry which prevents damage to the application R = 200 I/O when subjected to ESD surges up to 15 kV. C = 45 pF line TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 5 1/7 www.st.com 7Characteristics EMIF10-COM01F2 1 Characteristics Table 1. Absolute ratings (T = 25 C) amb Symbol Parameter and test conditions Value Unit 15 ESD discharge IEC61000-4-2, air discharge V kV PP ESD discharge IEC61000-4-2, contact discharge 8 T Junction temperature 125 C j T Operating temperature range - 40 to + 85 C op T Storage temperature range - 55 to + 150 C stg Table 2. Electrical characteristics (T = 25 C) amb Symbol Parameter I V Breakdown voltage BR I Leakage current V RM RM V Stand-off voltage RM V V V CL BR RM V Clamping voltage CL V I RM R Dynamic impedance d I R I Peak pulse current PP R Resistance between Input and Output I/O slope :1 / R d I PP C Input capacitance per line line Symbol Test conditions Min. Typ. Max. Unit V I = 1 mA 6 8 10 V BR R I V = 3 V per line 500 nA RM RM R I = 10 A, t = 2.5 s 1 d PP p R 180 200 220 I/O C At 0 V bias 45 50 pF line t V = 2.8 V R = 100 k 25 ns LH input load Figure 3. S21(db) attenuation Figure 4. Analog crosstalk (1) measurement 0.000.00 0.000.000.00 dBdB -10.00-10.00 dBdBdB -20.00-20.00 ---10.0010.0010.00 -30.00-30.00 ---20.0020.0020.00 -40.00-40.00 -50.00-50.00 ---30.0030.0030.00 -60.00-60.00 -70.00-70.00 ---40.0040.0040.00 -80.00-80.00 -90.00-90.00 ---50.0050.0050.00 -100.00-100.00 100.0k100.0k100.0k 1.0M1.0M1.0M 10.0M10.0M10.0M 100.0M100.0M100.0M 1.0G1.0G1.0G 100.0k100.0k 1.0M1.0M 10.0M10.0M 100.0M100.0M 1.0G1.0G f/Hzf/Hz f/Hzf/Hzf/Hz Xtalk 1/2 1. Spikes at high frequencies are induced by the PCB layout 2/7