HCF4017B DECADE COUNTER WITH 10 DECODED OUTPUTS MEDIUM SPEED OPERATION : 10 MHz (Typ.) at V = 10V DD FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO DIP SOP 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT I = 100nA (MAX) AT V = 18V T = 25C ORDER CODES I DD A 100% TESTED FOR QUIESCENT CURRENT PACKAGE TUBE T & R MEETS ALL REQUIREMENTS OF JEDEC DIP HCF4017BEY JESD13B STANDARD SPECIFICATIONS SOP HCF4017BM1 HCF4017M013TR FOR DESCRIPTION OF B SERIES CMOS DEVICE DESCRIPTION when the CLOCK INHIBIT signal is high. A high The HCF4017B is a monolithic integrated circuit RESET signal clears the counter to its zero count. fabricated in Metal Oxide Semiconductor Use of the Johnson decade-counter configuration technology available in DIP and SOP packages. permits high speed operation, 2-input decimal The HCF4017B is 5-stage Johnson counter decode gating and spike-free decoded outputs. having 10 decoded outputs. Inputs include a Anti-lock gating is provided, thus assuring proper CLOCK, a RESET, and a CLOCK INHIBIT signal. counting sequence. The decoded outputs are normally low and go high only at their respective Schmitt trigger action in the clock input circuit provides pulse shaping that allows unlimited clock decoded time slot. Each decoded output remains input pulse rise and fall times. This counter is high for one full clock cycle. A CARRY - OUT advanced one count at the positive clock signal signal completes one cycle every 10 clock input cycles and is used to ripple-clock the succeeding transition if the CLOCK INHIBIT signal is low. Counter advanced via the clock line is inhibited device in a multi-device counting chain. PIN CONNECTION September 2001 1/11HCF4017B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 3, 2, 4, 7, 10, 0 to 9 Decoded Decimal Output 1, 5, 6, 9, 11 14 CLOCK Clock Input CLOCK 13 Clock Inhibit Input INHIBIT 15 RESET Reset Input 12 CARRY OUT Carry Output V 8 Negative Supply Voltage SS V 16 Positive Supply Voltage DD TRUTH TABLE FUNCTIONAL DIAGRAM CLOCK DECODED CLOCK RESET INHIBIT OUTPUT Q XXH 0 Q LX L n Q XH L n Q LL n+1 Q LL n HLQ n Q HL n+1 X : Dont Care Qn : No Change LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11