M41ST87W 5.0 and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM Datasheet - production data Two independent power-fail comparators (1.25 V reference) Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, 28-pin, (300 mil) year, and century SOX28, embedded crystal 128 bytes of clearable, general purpose NVRAM Programmable alarm and interrupt function (valid even during battery backup mode) Programmable watchdog timer SSOP20 Unique electronic serial number (8-byte) 32 kHz frequency output available upon power-on Features Microprocessor power-on reset output 5.0, 3.3, or 3.0 V operation 2 Battery low flag 400 kHz I C bus Ultra-low battery supply current of 500 nA NVRAM supervisor to non-volatize external (typ) LPSRAM 2.5 to 5.5 V oscillator operating voltage Security features Automatic switchover and deselect circuitry Choice of power-fail deselect voltages Tamper indication circuits with timestamp M41ST87Y: (not recommended for new and RAM clear design, contact ST sales office for LPSRAM clear function (TP ) CLR availability) Packaging includes a 28-lead, embedded THS = 1: V 4.63 V crystal SOIC and a 20-lead SSOP PFD V = 4.75 to 5.5 V CC Oscillator stop detection THS = 0: V 4.37 V PFD V = 4.5 to 5.5 V CC M41ST87W: THS = 1: V 2.9 V PFD V = 3.0 to 3.6 V CC THS = 0: V 2.63 V PFD V = 2.7 to 3.6 V CC May 2016 DocID9497 Rev 11 1/54 www.st.com This is information on a product in full production. Contents M41ST87W Contents 1 Description....................................................................................... 6 2 Operating modes ........................................................................... 12 2.1 2-wire bus characteristics ................................................................ 13 2.1.1 Bus not busy ..................................................................................... 13 2.1.2 Start data transfer ............................................................................. 13 2.1.3 Stop data transfer ............................................................................. 13 2.1.4 Data valid .......................................................................................... 13 2.1.5 Acknowledge .................................................................................... 13 2.2 READ mode .................................................................................... 15 2.3 WRITE mode ................................................................................... 17 2.4 Data retention mode ........................................................................ 17 2.5 Tamper detection circuit .................................................................. 18 2.6 Tamper register bits (tamper 1 and tamper 2) ................................. 18 2.6.1 Tamper enable bits (TEB1 and TEB2) ............................................. 18 2.6.2 Tamper bits (TB1 and TB2) .............................................................. 18 2.6.3 Tamper interrupt enable bits (TIE1 and TIE2) .................................. 19 2.6.4 Tamper connect mode bit (TCM1 and TCM2) ................................. 19 2.6.5 Tamper polarity mode bits (TPM1 and TPM2) ................................. 19 2.6.6 Tamper detect sampling (TDS1 and TDS2) ..................................... 21 2.6.7 Tamper current high/tamper current low (TCHI/ 1 and TCHI/ 2) .................................................................................................... 21 2.6.8 RAM clear (CLR1 and CLR2) ........................................................... 21 2.6.9 RAM clear external (CLR1 and CLR2 ) - available in SOX28 EXT EXT package only .................................................................................................... 21 2.7 Tamper detection operation ............................................................ 25 2.8 Sampling ......................................................................................... 25 2.9 Internal tamper pull-up/down current ............................................... 26 2.10 Avoiding inadvertent tampers (normally closed configuration) ........ 26 2.11 Tamper event time-stamp ............................................................... 27 3 Clock operation ............................................................................. 28 3.1 Power-down time-stamp ................................................................. 28 3.2 TIMEKEEPER registers................................................................. 29 3.3 Calibrating the clock ........................................................................ 31 3.4 Setting alarm clock registers ........................................................... 32 3.5 Watchdog timer ............................................................................... 34 2/54 DocID9497 Rev 11