M41ST87Y M41ST87W 5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM Features Embedded crystal 5.0, 3.3, or 3.0 V operation 2 400 kHz I C bus NVRAM supervisor to non-volatize external LPSRAM 2.5 to 5.5 V oscillator operating voltage 28-pin, (300 mil) Automatic switchover and deselect circuitry SOX28 Choice of power-fail deselect voltages M41ST87Y: (not recommended for new design, contact ST sales office for availability) THS = 1: V 4.63 V V = 4.75 to 5.5 V PFD CC THS = 0: V 4.37 V V = 4.5 to 5.5 V PFD CC M41ST87W: SSOP20 THS = 1: V 2.9 V V = 3.0 to 3.6 V PFD CC THS = 0: V 2.63 V V = 2.7 to 3.6 V PFD CC Two independent power-fail comparators Security features (1.25 V reference) Tamper indication circuits with timestamp and Counters for tenths/hundredths of seconds, RAM clear seconds, minutes, hours, day, date, month, year, and century LPSRAM clear function (TP ) CLR 128 bytes of clearable, general purpose Packaging includes a 28-lead, embedded NVRAM crystal SOIC and a 20-lead SSOP Programmable alarm and interrupt function Oscillator stop detection (valid even during battery backup mode) Programmable watchdog timer Unique electronic serial number (8-byte) 32 kHz frequency output available upon power- on Microprocessor power-on reset output Battery low flag Ultra-low battery supply current of 500 nA (typ) October 2011 Doc ID 9497 Rev 10 1/54 www.st.com 1Contents M41ST87Y, M41ST87W Contents 1 Description . 6 1.1 Security features 6 2 Operating modes . 12 2.1 2-wire bus characteristics . 13 2.1.1 Bus not busy . 13 2.1.2 Start data transfer . 13 2.1.3 Stop data transfer . 13 2.1.4 Data valid 13 2.1.5 Acknowledge . 13 2.2 READ mode . 15 2.3 WRITE mode 17 2.4 Data retention mode . 17 2.5 Tamper detection circuit 18 2.6 Tamper register bits (tamper 1 and tamper 2) . 18 2.6.1 Tamper enable bits (TEB1 and TEB2) 18 2.6.2 Tamper bits (TB1 and TB2) 19 2.6.3 Tamper interrupt enable bits (TIE1 and TIE2) 19 2.6.4 Tamper connect mode bit (TCM1 and TCM2) 19 2.6.5 Tamper polarity mode bits (TPM1 and TPM2) 19 2.6.6 Tamper detect sampling (TDS1 and TDS2) 22 2.6.7 Tamper current high/tamper current low (TCHI/TCLO1 and TCHI/TCLO2) . 22 2.6.8 RAM clear (CLR1 and CLR2) 22 2.6.9 RAM clear external (CLR1 and CLR2 ) - available in SOX28 EXT EXT package only . 22 2.7 Tamper detection operation . 26 2.8 Sampling . 26 2.9 Internal tamper pull-up/down current 27 2.10 Avoiding inadvertent tampers (normally closed configuration) . 27 2.11 Tamper event time-stamp . 28 3 Clock operation 29 3.0.1 Power-down time-stamp 29 2/54 Doc ID 9497 Rev 10